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ds07-13502-5e fujitsu semiconductor data sheet 16-bit proprietary microcontroller cmos f 2 mc-16f mb90220 series mb90223/224/p224a/w224a mb90p224b/w224b/v220 n outline the mb90220 series of general-purpose high-performance 16-bit microcontrollers has been developed primarily for applications that demand high-speed real-time processing and is suited for industrial applications, office automation equipment, process control, and other applications. the f 2 mc-16f cpu is based on the f 2 mc*-16 family with improved high-level language support functions and task switching functions, as well as additional addressing modes. on-chip peripheral resources include a 4-channel pwc timer, a 4-channel icu (input capture unit), a 1-channel 24-bit timer counter, an 8-channel ocu (output compare unit), a 6-channel 16-bit reload timer, a 2-channel 16-bit ppg timer, a 10-bit a/d converter with 16 inputs, and a 4-channel serial port with a uart function (one channel includes the cts function). the mb90p224b, mb90w224b, mb90224 is under development. *: f 2 mc stands for fujitsu flexible microcontroller. n pac k ag e 120-pin plastic qfp (fpt-120p-m03) 120-pin ceramic qfp (fpt-120c-c02)
mb90220 series 2 n features f 2 mc-16f cpu ? minimum execution time: 62.5 ns/16 mhz oscillation (using a duty control system) ? instruction sets optimized for controllers upward object-compatible with the f 2 mc-16(h) various data types (bit, byte, word, and long-word) instruction cycle improved to speed up operation extended addressing modes: 25 types high coding efficiency access method (bank access with linear pointer) enhanced multiplication and division instructions (with signed instructions added) higher-precision operation using a 32-bit accumulator ? extended intelligent i/o service (automatic transfer function independent of instructions) access area expanded to 64 kbytes ? enhanced instruction set applicable to high-level language (c) and multitasking system stack pointer enhanced pointer-indirect instructions barrel shift instruction stack check function ? increased execution speed: 8-byte instruction queue ? powerful interrupt functions: 8 levels and 28 sources peripheral resources ? mask rom : 64 kbytes (mb90223) 96 kbytes (mb90224) eprom : 96 kbytes (mb90w224a/w224b) ? one-time prom : 96 kbytes (MB90P224A/p224b) ? ram: 3 kbytes (mb90223) 4.5 kbytes (mb90224/mb90w224a/p224a/w224b/p224b) 5 kbytes (mb90v220) ? general-purpose ports: max. 102 channels ? icu (input capture unit): 4 channels ? 24-bit timer counter: 1 channel ? ocu (output compare unit): 8 channels ? pwc timer with time measurement function: 4 channels ? 10-bit a/d converter: 16 channels ? uart: 4 channels (one channel includes cts function) ? 16-bit reload timer toggled output, external clock, and gate functions: 6 channels ? 16-bit ppg timer: 2 channels ? dtp/external-interrupt inputs: 8 channels (of which five have edge detection function only) ? write-inhibit ram: 0.5 kbytes (1 kbyte for mb90v220) ? timebase counter: 18 bits ? clock gear function ? low-power consumption mode sleep mode stop mode hardware standby mode
3 mb90220 series product description ? mb90223/224 are mask rom product. ? MB90P224A/p224b are one-time prom products. ? mb90w224a/w224b are eprom products. es only. ? operating temperature of MB90P224A/w224a is C40 c to +85 c. (however, the ac characteristics is assured in C40 c to +70 c) ? operation clock cycle of mb90223 is 10 mhz to 12 mhz. ? mb90v220 is a evaluation device for the program development. es only. n product lineup (continued) mb90223 mb90224 MB90P224A mb90p224b mb90w224a mb90w224b mb90v220 classification mask rom product mask rom product one-time prom product eprom product evaluation device rom size 64 kbytes 96 kbytes 96 kbytes 96 kbytes none ram size 3 kbytes 4.5 kbytes 4.5 kbytes 4.5 kbytes 5 kbytes cpu functions the number of instructions: 412 instruction bit length: 8 or 16 bits instruction length: 1 to 7 bytes data bit length: 1, 4, 8, 16, or 32 bits minimum execution time: 62.5 ns/16 mhz interrupt processing time: 1.0 m s/16 mhz (min.) ports i/o ports (n-ch open-drain): 16 i/o ports (cmos): 86 to t a l : 1 0 2 icu (input capture unit) number of channels: 4 rising edge/falling edge/both edges selectable 24-bit timer counter number of channels: 1 overflow interrupt, intermediate bit interrupt ocu (output compare unit) number of channels: 8 pin change source (match signal causes register value transfer/general-purpose port) pwc timer number of channels: 4 16-bit reload timer operation (operation clock cycle: 0.25 m s to 1.31 ms) 16-bit pulse-width count operation (allowing continuous/one-shot measurement, h/l width measurement, inter-edge measurement, and divided-frequency measurement) 10-bit a/d converter resolution: 10 bits number of inputs: 16 single conversion mode (conversion of each channel) scan conversion mode (continuous conversion for up to 16 consecutive channels) continuous conversion mode (repeated conversion of specified channel) stop conversion mode (conversion every fixed cycle) uart number of channels: 4 (1 channel with cts function) clock-synchronous transfer mode (full-duplex double buffering, 7 to 9-bit data length, 2400 to 62500 bps) asynchronous transfer mode (full-duplex double buffering, 7 to 9-bit data length, 2400 to 62500 bps) 16-bit reload timer number of channels: 6 16-bit reload timer operation (operation clock cycle: 0.25 m s to 1.05 s) part number item
mb90220 series 4 (continued) note: mb90v220 is a evaluation device, therefore, the electrical characteristics are not assured. n differences between mb90223/224 (mask rom product) and MB90P224A/ w224a/p224b/w224b mb90223 mb90224 MB90P224A mb90p224b mb90w224a mb90w224b mb90v220 16-bit ppg timer number of channels: 2 16-bit ppg operation (operation clock cycle: 0.25 m s to 6 s) dtp/external interrupts number of inputs: 8 (of which five have edge detection function only) external interrupt mode (allowing interrupts to activate at four different request levels) simple dma transfer mode (allowing extended i 2 os to activate at two different request levels) write-inhibited ram ram size: 512 bytes (1 kbyte for mb90v220) ram write-protectable with wi pin standby mode stop mode (activated by software or hardware) and sleep mode gear function machine clock operation frequency switching: 16 mhz, 8 mhz, 4 mhz, 1 mhz (at 16-mhz oscillation) package fpt-120p-m03 fpt-120c-c02 pga-256c-a02 mb90223 mb90224 MB90P224A mb90p224b mb90w224a mb90w224b rom mask rom 64 kbytes mask rom 96 kbytes otprom 96 kbytes eprom 96 kbytes pin functions: pin 87 md2 pin md2/v pp pin part number item part number item
5 mb90220 series n pin assignment p01/d01 96 p02/d02 97 p03/d03 98 p04/d04 99 p05/d05 100 p06/d06 101 p07/d07 102 p10/d08 103 p11/d09 104 p12/d10 105 p13/d11 106 p14/d12 107 p15/d13 108 p16/d14 109 p17/d15 110 p20/a00 111 p21/a01 112 p22/a02 113 p23/a03 114 p24/a04 115 p25/a05 116 p26/a06 117 p27/a07 118 v ss 119 p30/a08 120 60 pa5/int0 59 pa4/pwc3/pot3/asr3 58 pa3/pwc2/pot2/asr2 57 pa2/pwc1/pot1/asr1 56 pa1/pwc0/pot0 55 pa0/asr0 54 v cc 53 p67/an07 52 p66/an06 51 p65/an05 50 p64/an04 49 p63/an03 48 p62/an02 47 p61/an01 46 p60/an00 45 av ss 44 avrl 43 avrh 42 av cc 41 p97/an15 40 p96/an14 39 p95/an13 38 p94/an12 37 p93/an11 36 p92/an10 35 p91/an09 34 p90/an08 33 v ss 32 p87/ppg1 31 p86/ppg0 v ss 91 x0 92 x1 93 v cc 94 p00/d00 95 p31/a09 1 p32/a10 2 p33/a11 3 p34/a12 4 p35/a13 5 p36/a14 6 p37/a15 7 v cc 8 p40/a16 9 p41/a17 10 p42/a18 11 p43/a19/tin1/int3 12 p44/a20/tin2/int4 13 p45/a21/tin3/int5 14 p46/a22/tin4/int6 15 p47/a23/tin5/int7 16 p70/dot0 17 p71/dot1 18 p72/dot2 19 p73/dot3 20 p74/dot4 21 p75/dot5 22 p76/dot6 23 p77/dot7 24 p80/tot0 25 p81/tot1 26 p82/tot2 27 p83/tot3 28 p84/tot4 29 p85/tot5 30 90 rst 89 md0 88 md1 87 md2 86 hst 85 p57/wi 84 p56/rd 83 p55/wrl 82 p54/wrh 81 p53/hrq 80 p52/hak 79 p51/rdy 78 p50/clk 77 pc5/trg0 76 pc4/cts0 75 pc3/sck3 74 pc2/sid3 73 pc1/sod3 72 pc0/sck2 71 pb7/sid2 70 pb6/sod2 69 pb5/sck1 68 pb4/sid1 67 pb3/sod1 66 pb2/sck0 65 pb1/sid0 64 pb0/sod0 63 v ss 62 pa7/int2/atg 61 pa6/int1 (top view) (fpt-120p-m03) (fpt-120c-c02)
mb90220 series 6 n pin description * : fpt-120p-m03, fpt-120c-c02 (continued) pin no. pin name circuit type function qfp* 92, 93 x0, x1 a crystal oscillation pins (16 mhz) 89 to 87 md0 to md2 d operation mode specification input pins connect directly to v cc or v ss . 90 rst g external reset request input 86 hst e hardware standby input pin 95 to 102 p00 to p07 c general-purpose i/o ports this function is valid only in single-chip mode. d00 to d07 output pins for low-order 8 bits of the external address bus. this function is valid only in modes where the external bus is enabled. 103 to 110 p10 to p17 c general-purpose i/o ports this function is valid only in single-chip mode or when the external bus is enabled and the 8-bit data bus specification has been made. d08 to d15 i/o pins for higher-order 8 bits of the external data bus this function is valid only when the external bus is enabled and the 16-bit bus specification has been made. 111 to 118 p20 to p27 c general-purpose i/o ports this function is valid only in single-chip mode. a00 to a07 output pins for lower-order 8 bits of the external address bus this function is valid only in modes where the external bus is enabled. 120, 1 to 7 p30, p31 to p37 c general-purpose i/o ports this function is valid either in single-chip mode or when the address mid-order control register specification is port. a08, a09 to a15 output pins for mid-order 8 bits of the external address bus this function is valid in modes where the external bus is enabled and the address mid-order control register specification is address. 9 to 11 p40 to p42 c general-purpose i/o ports this function is valid either in single-chip mode or when the address high-order control register specification is port. a16 to a18 output pins for higher-order 8 bits of the external address bus this function is valid in modes where the external bus is enabled and the address high-order control register specification is address. 12 to 16 p43 to p47 c general-purpose i/o ports this function is valid when either single-chip mode is enabled or the address higher-order control register specification is port. a19 to a23 output pins for higher-order 8 bits of the external address bus this function is valid in modes where the external bus is enabled and the address higher-order control register specification is address. tin1 to tin5 16-bit reload timer input pins this function is valid when the timer input specification is enabled. the data on the pins is read as timer input (tin1 to tin5).
7 mb90220 series * : fpt-120p-m03, fpt-120c-c02 (continued) pin no. pin name circuit type function qfp* 12 to 16 int3 to int7 c external interrupt request input pins when external interrupts are enabled, these inputs may be used suddenly at any time; therefore, it is necessary to stop output by other functions on these pins, except when using them for output deliberately. 78 p50 c general-purpose i/o port this function is valid in single-chip mode and when the clk output specification is disabled. clk clk output pin this function is valid in modes where the external bus is enabled and the clk output specification is enabled. 79 p51 c general-purpose i/o port this function is valid in single-chip mode or when the ready function is disabled. rdy ready input pin this function is valid in modes where the external bus is enabled and the ready function is enabled. 80 p52 c general-purpose i/o port this function is valid in single-chip mode or when the hold function is disabled. hak hold acknowledge output pin this function is valid in modes where the external bus is enabled and the hold function is enabled. 81 p53 c general-purpose i/o port this function is valid in single-chip mode or external bus mode and when the hold function is disabled. hrq hold request input pin this function is valid in modes where the external bus is enabled and the hold function is enabled. during this operation, the input may be used suddenly at any time; therefore, it is necessary to stop output by other fuctions on this pin, except when using it for output deliberately. 82 p54 c general-purpose i/o port this function is valid in single-chip mode, when the external bus is in 8-bit mode, or when wrh pin output is disabled. wrh write strobe output pin for the high-order 8 bits of the data bus this function is valid in modes where the external bus is enabled, the external bus is in 16-bit mode, and wrh pin output is enabled. 83 p55 c general-purpose i/o port this function is valid in single-chip mode or when wrl pin output is disabled. wrl write strobe output pin for the low-order 8 bits of the data bus this function is valid in modes where the external bus is enabled and wrl pin output is enabled.
mb90220 series 8 * : fpt-120p-m03, fpt-120c-c02 (continued) pin no. pin name circuit type function qfp* 84 p56 c general-purpose i/o port this function is valid in single-chip mode. this function is valid in modes where the external bus is valid. rd read strobe output pin for the data bus this function is valid in modes where the external bus is enabled. 85 p57 b general-purpose i/o port this function is always valid. when these pins are open in input mode, through current may leak in stop mode/reset mode, be sure to fix these pins to v cc /v ss level to use these pins in input mode. wi ram write disable request input during this operation, the input may be used suddenly at any time; therefore, it is necessary to stop output by other fuctions on this pin, except when using it for output deliberately. 46 to 53 p60 to p67 f open-drain i/o ports this function is valid when the analog input enable register specification is port. an00 to an07 10-bit a/d converter analog input pins this function is valid when the analog input enable register specification is analog input. 17 to 24 p70 to p77 c general-purpose i/o ports this function is valid when the output specification for dot0 to dot7 is disabled. dot0 to dot7 this function is valid when ocu (output compare unit) output is enabled. 25 to 30 p80 to p85 c general-purpose i/o ports this function is valid when the output specification for tot0 to tot5 is disabled. tot0 to tot5 16-bit reload timer output pins (tot0 to tot5) 31, 32 p86, p87 c general-purpose i/o ports this function is valid when the ppg0, and ppg1 output specification is disabled. ppg0, ppg1 16-bit ppg timer output pins this function is valid when the ppg control/status register specification is ppg output pins. 34 to 41 p90 to p97 f open-drain i/o ports this function is valid when the analog input enable register specification is port. an08 to an15 10-bit a/d converter analog input pins this function is valid when the analog input enable register specification is analog input.
9 mb90220 series * : fpt-120p-m03, fpt-120c-c02 (continued) pin no. pin name circuit type function qfp* 55 pa0 c general-purpose i/o port this function is always valid. asr0 icu (input capture unit) input pin this function is valid during icu (input capture unit) input operations. 56 pa1 c general-purpose i/o port this function is always valid. pwc0 pwc input pin during pwc0 input operations, this input may be used suddenly at any time; therefore, it is necessary to stop output by other functions on this pin, except when using it for output deliberately. pot0 pwc output pin this function is valid during pwc output operations. 57 to 59 pa2 to pa4 c general-purpose i/o ports this function is always valid. pwc1 to pwc3 pwc input pins this function is valid during pwc input operations. during pwc1 to pwc3 input operations, this input may be used suddenly at any time; therefore, it is necessary to stop output by other functions on this pin, except when using it for output deliberately. pot1 to pot3 pwc output pins this function is valid during pwc output operations. asr1 to asr3 icu (input capture unit) input pins this function is valid during icu (input capture unit) input operations. 60, 61 pa 5 , pa 6 b general-purpose i/o ports this function is always valid. when these pins are open in input mode, through current may leak in stop mode/reset mode, be sure to fix these pins to v cc /v ss level to use these pins in input mode. int0, int1 dtp/external interrupt request input pins when dtp/external interrupts are enabled, these inputs may be used suddenly at any time; therefore, it is necessary to stop output by other functions on these pins, except when using them for output deliberately. when these pins are open in input mode, through current may leak in stop mode/reset mode, be sure to fix these pins to v cc /v ss level to use these pins in input mode. 62 pa7 b general-purpose i/o port this function is always valid. when these pins are open in input mode, through current may leak in stop mode/reset mode, be sure to fix these pins to v cc /v ss level to use these pins in input mode.
mb90220 series 10 * : fpt-120p-m03, fpt-120c-c02 (continued) pin no. pin name circuit type function qfp* 62 int2 b dtp/external interrupt request input pin when dtp/external interrupts are enabled, these inputs may be used suddenly at any time; therefore, it is necessary to stop output by other functions on these pins, except when using them for output deliberately. when these pins are open in input mode, through current may leak in stop mode/reset mode, be sure to fix these pins to v cc /v ss level to use these pins in input mode. at g 10-bit a/d converter external trigger input pin when these pins are open in input mode, through current may leak in stop mode/reset mode, be sure to fix these pins to v cc /v ss level to use these pins in input mode. 64 pb0 c general-purpose i/o port this function is valid when the uart0 (ch.0) serial data output specification is disabled. sod0 uart0 (ch.0) serial data output this function is valid when the uart0 (ch.0) serial data output specification is enabled. 65 pb1 c general-purpose i/o port this function is always valid. sid0 uart0 (ch.0) serial data input pin during uart0 (ch.0) input operations, this input may be used suddenly at any time; therefore, it is necessary to stop output by other functions on this pin, except when using it for output deliberately. 66 pb2 c general-purpose output port this function is valid when the uart0 (ch.0) clock output specification is disabled. sck0 uart0 (ch.0) clock output pin the clock output function is valid when the uart0 (ch.0) clock output specification is enabled. uart0 (ch.0) external clock input pin. this function is valid when the port is in input mode and the uart0 (ch.0) specification is external clock mode. 67 pb3 c general-purpose i/o port this function is valid when the uart0 (ch.1) serial data output specification is disabled. sod1 uart0 (ch.1) serial data output pin this function is valid when the uart0 (ch.1) serial data output specification is enabled. 68 pb4 c general-purpose i/o port this function is always valid. sid1 uart0 (ch.1) serial data input pin during uart0 (ch.1) input operations, this input may be used suddenly at any time; therefore, it is necessary to stop output by other functions on this pin, except when using it for output deliberately.
11 mb90220 series * : fpt-120p-m03, fpt-120c-c02 (continued) pin no. pin name circuit type function qfp* 69 pb5 c general-purpose i/o port this function is valid when the uart0 (ch.1) clock output specification is disabled. sck1 uart0 (ch.1) clock output pin the clock output function is valid when the uart0 (ch.1) clock output specification is enabled. uart0 (ch.1) external clock input pin this function is valid when the port is in input mode and the uart0 (ch.1) specification is external clock mode. 70 pb6 c general-purpose i/o port this function is valid when the uart0 (ch.2) serial data output specification is disabled. sod2 uart0 (ch.2) serial data output pin this function is valid when the uart0 (ch.2) serial data output specification is enabled. 71 pb7 c general-purpose i/o port this function is always valid. sid2 uart0 (ch.2) serial data input pin during uart0 (ch.2) input operations, this input may be used suddenly at any time; therefore, it is necessary to stop output by other functions on this pin, except when using it for output deliberately. 72 pc0 c general-purpose i/o port this function is valid when the uart0 (ch.2) clock output specification is disabled. sck2 uart0 (ch.2) clock output pin the clock output function is valid when the uart0 (ch.2) clock output specification is enabled. uart0 (ch.2) external clock input pin this function is valid when the port is in input mode and the uart0 (ch.2) specification is external clock mode. 73 pc1 c general-purpose i/o port this function is valid when the uart1 serial data output specification is disabled. sod3 uart1 serial data output pin this function is valid when the uart1 serial data output specification is enabled. 74 pc2 c general-purpose i/o port this function is always valid. sid3 uart1 serial data input pin during uart1 input operations, this input may be used suddenly at any time; therefore, it is necessary to stop output by other functions on this pin, except when using it for output deliberately.
mb90220 series 12 (continued) * : fpt-120p-m03, fpt-120c-c02 (continued) pin no. pin name circuit type function qfp* 75 pc3 c general-purpose i/o port this function is valid when the uart1 clock output specification is disabled. sck3 uart1 clock output pin the clock output function is valid when the uart1 clock output specification is enabled. uart1 external clock input pin this function is valid when the port is in input mode and the uart1 specification is external clock mode. 76 pc4 c general-purpose i/o port this function is always valid. cts0 uart0 (ch.0) clear to send input pin when the uart0 (ch.0) cts function is enabled, this input may be used suddenly at any time; therefore, it is necessary to stop output by other functions on this pin, except when using it for output deliberately. 77 pc5 c general-purpose i/o port this function is always valid. trg0 16-bit ppg timer trigger input pin this function is valid when the 16-bit ppg timer trigger input specification is enabled. the data on this pin is read as 16-bit ppg timer trigger input (trg0). during this operation, the input may be used suddenly at any time; therefore, it is necessary to stop output by other functions on this pin, except when using it for output deliberately. 8, 54, 94 v cc power supply power supply for digital circuitry 33, 63, 91, 119 v ss power supply ground level for digital circuitry 42 av cc power supply power supply for analog circuitry when turning this power supply on or off, always be sure to first apply electric potential equal to or greater than av cc to v cc . during normal operation av cc should be equal to v cc . 43 avrh power supply reference voltage input for analog circuitry when turning this pin on or off, always be sure to first apply electric potential equal to or greater than avrh to av cc . 44 avrl power supply reference voltage input for analog circuitry 45 av ss power supply ground level for analog circuitry
13 mb90220 series n i/o circuit type note: the pull-up and pull-down resistors are always connected, regardless of the state. (continued) type circuit remarks a ? oscillation feedback resistor: approx. 1 m w mb90223 mb90224 mb90p224b mb90w224b ? oscillation feedback resistor: approx. 1 m w MB90P224A mb90w224a b ? cmos-level output ? cmos-level hysteresis input with no standby control x1 x0 standby control signal x1 x0 standby control signal digital output digital output digital input r
mb90220 series 14 note: the pull-up and pull-down resistors are always connected, regardless of the state. (continued) type circuit remarks c ? cmos-level output ? cmos-level hysteresis input with standby control d ? cmos-level input with no standby control mask rom products only: md2: with pull-down resistor md1: with pull-up resistor md0: with pull-down resistor ? cmos-level input with no standby control md2 of otprom products/eprom products only e ? cmos-level hysteresis input with no standby control ? with input analog filter (40 ns typ.) digital output digital output digital input r digital input r vpp power supply digital input r digital input r analog filter
15 mb90220 series (continued) note: the pull-up and pull-down resistors are always connected, regardless of the state. type circuit remarks f ? n-channel open-drain output ? cmos-level hysteresis input with a/d control and with standby control g ? cmos-level hysteresis input with no standby control and with pull-up resistor ? with input analog filter (40 ns typ.) mb90223, mb90224: rst pin can be set to with or without a pull-up resistor by a mask option. MB90P224A: with pull-up resistor mb90w224a: with pull-up resistor mb90p224b: with no pull-up resistor mb90w224b: with no pull-up resistor digital output a/d input r digital input digital input r r analog filter pull-up resistor : p-type transistor : n-type transistor
mb90220 series 16 n handling devices 1. preventing latchup cmos ics may cause latchup when a voltage higher than v cc or lower than v ss is applied to input or output pins other than medium-and high-voltage pins, or when a voltage exceeding the rating is applied between v cc and v ss . if latch-up occurs, the power supply current increases rapidly, sometimes resulting in thermal breakdown of the device. use meticulous care not to let any voltage exceed the maximum rating. also, take care to prevent the analog power supply (av cc and avrh) and analog input from exceeding the digital power supply (v cc ) when the analog system power supply is turned on and off. 2. treatment of unused input pins leaving unused input pins open could cause malfunctions. they should be connected to a pull-up or pull-down resistor. 3. treatment of pins when a/d is not used connect to be av cc = avrh = v cc and av ss = avrl = v ss even if the a/d converter is not in use. 4. precautions when using an external input to reset the internal circuit properly by the l level input to the rst pin, the l level input to the rst pin must be maintained for at least five machine cycles. pay attention to it if the chip uses external clock input. 5. v cc and v ss pins apply equal potential to the v cc and v ss pins. 6. supply voltage variation the operation assurance range for the v cc supply voltage is as given in the ratings. however, sudden changes in the supply voltage can cause misoperation, even if the voltage remains within the rated range. therefore, it is important to supply a stable voltage to the ic. the recommended power supply control guidelines are that the commercial frequency (50 to 60 hz) ripple variation (p-p value) on v cc should be less than 10% of the standard v cc value and that the transient rate of change during sudden changes, such as during power supply switching, should be less than 0.1 v/ms. 7. notes on using an external clock when using an external clock, drive the x0 pin as illustrated below. when an external clock is used, oscillation stabilization time is required even for power-on reset and wake-up from stop mode. use of external clock x0 x1 mb90220 note: when using an external clock, be sure to input external clock more than 6 machine cycles after setting the hst pin to l to transfer to the hardware standby mode.
17 mb90220 series 8. power-on sequence for a/d converter power supplies and analog inputs be sure to turn on the digital power supply (v cc ) before applying voltage to the a/d converter power supplies (av cc , avrh, and avrl) and analog inputs (an00 to an15). when turning power supplies off, turn off the a/d converter power supplies (av cc , avrh, and avrl) and analog inputs (an00 to an15) first, then the digital power supply (v cc ). when turning avrh on or off, be careful not to let it exceed av cc .
mb90220 series 18 n programming for MB90P224A/p224b/w224a/w224b in eprom mode, the MB90P224A/p224b/w224a/w224b functions equivalent to the mbm27c1000. this allows the eprom to be programmed with a general-purpose eprom programmer by using the dedicated socket adapter (do not use the electronic signature mode). 1. program mode when shipped from fujitsu, and after each erasure, all bits (96 k 8 bits) in the MB90P224A/p224b/w224a/ w224b are in the 1 state. data is written to the rom by selectively programming 0s into the desired bit locations. bits cannot be set to 1 electrically. 2. programming procedure (1) set the eprom programmer to mbm27c1000. (2) load program data into the eprom programmer at 08000 h to 1ffff h . note that rom addresses fe8000 h to ffffff h in the operation mode in the MB90P224A/p224b/w224a/ w224b series assign to 08000 h to 1ffff h in the eprom mode (on the eprom programmer). (3) mount the MB90P224A/p224b/w224a/w224b on the adapter socket, then fit the adapter socket onto the eprom programmer. when mounting the device and the adapter socket, pay attention to their mounting orientations. (4) start programming the program data to the device. (5) if programming has not successfully resulted, connect a capacitor of approx. 0.1 m f between v cc and gnd, between v pp and gnd. note: the mask rom products (mb90223, mb90224) does not support eprom mode. data cannot, therefore, be read by the eprom programmer. ffffff h 08000 h * 1ffff h * operation mode * : be sure to set the programming, the start address and the stop address on the eprom programmer to 08000 h /1ffff h . eprom mode (corresponding addresses on the eprom mode) fe8000 h
19 mb90220 series 3. eprom programmer socket adapter and recommended programmer manufacturer inquiry: sun hayato co., ltd.: tel: (81)-3-3986-0403 fax: (81)-3-5396-9106 advantest corp.: tel: except japan (81)-3-3930-4111 4. erase procedure data written in the mb90w224a/w224b is erased (from 0 to 1) by exposing the chip to ultraviolet rays with a wavelength of 2,537 ? through the translucent cover. recommended irradiation dosage for exposure is 10 wsec/cm 2 . this amount is reached in 15 to 20 minutes with a commercial ultraviolet lamp positioned 2 to 3 cm above the package (when the package surface illuminance is 1200 m w/cm 2 ). if the ultraviolet lamp has a filter, remove the filter before exposure. attaching a mirrored plate to the lamp increases the illuminance by a factor of 1.4 to 1.8, thus shortening the required erasure time. if the translucent part of the package is stained with oil or adhesive, transmission of ultraviolet rays is degraded, resulting in a longer erasure time. in that case, clean the translucent part using alcohol (or other solvent not affecting the package). the above recommended dosage is a value which takes the guard band into consideration and is a multiple of the time in which all bits can be evaluated to have been erased. observe the recommended dosage for erasure; the purpose of the guard band is to ensure erasure in all temperature and supply voltage ranges. in addition, check the life span of the lamp and control the illuminance appropriately. data in the mb90w224a/w224b is erased by exposure to light with a wavelength of 4,000 ? or less. data in the device is also erased even by exposure to fluorescent lamp light or sunlight although the exposure results in a much lower erasure rate than exposure to 2,537 ? ultraviolet rays. note that exposure to such lights for an extended period will therefore affect system reliability. if the chip is used where it is exposed to any light with a wavelength of 4,000 ? or less, cover the translucent part, for example, with a protective seal to prevent the chip from being exposed to the light. exposure to light with a wavelength of 4,000 to 5,000 ? or more will not erase data in the device. if the light applied to the chip has a very high illuminance, however, the device may cause malfunction in the circuit for reasons of general semiconductor characteristics. although the circuit will recover normal operation when exposure is stopped, the device requires proper countermeasures for use in a place exposed continuously to such light even though the wavelength is 4,000 ? or more. part no. mb90p224b package qfp-120 compatible socket adapter sun hayato co., ltd. rom-120qf-32dp-16f recommended programmer manufacturer and programmer name advantest corp. r4945a (main unit) + r49451a (adapter) recommended
mb90220 series 20 5. recommended screening conditions high temperature aging is recommended as the pre-assembly screening procedure. 6. programming yeild MB90P224A/p224b cannot be write-tested for all bits due to their nature. therefore the write yield cannot always be guaranteed to be 100%. 7. pin assignments in eprom mode (1) pins compatible with mbm27c1000 mbm27c1000 MB90P224A/p224b/ mb90w224a/w224b mbm27c1000 MB90P224A/p224b/ mb90w224a/w224b pin no. pin name pin no. pin name pin no. pin name pin no. pin name 1v pp 87 md2 (v pp )32v cc 8, 54, 94 v cc 2oe 83p55 31pgm 84p56 3 a15 7 p37 30 n.c. 4 a12 4 p34 29 a14 6 p36 5 a07 118 p27 28 a13 5 p35 6 a06 117 p26 27 a08 120 p30 7 a05 116 p25 26 a09 1 p31 8 a04 115 p24 25 a11 3 p33 9 a03 114 p23 24 a16 9 p40 10 a02 113 p22 23 a10 2 p32 11 a01 112 p21 22 ce 82 p54 12 a00 111 p20 21 d07 102 p07 13 d00 95 p00 20 d06 101 p06 14 d01 96 p01 19 d05 100 p05 15 d02 97 p02 18 d04 99 p04 16 gnd 33, 63, 91,119 v ss 17 d03 98 p03 program, verify aging +150 c, 48 hrs. data verification assembly
21 mb90220 series (2) power supply and gnd connection pins (3) pins other than mbm27c1000-compatible pins type pin no. pin name power supply 89 88 86 8, 54, 94 md0 md1 hst v cc gnd 33, 63, 91, 119 44 45 80 81 90 v ss avrl av ss p52 p53 rst pin no. pin name treatment 92 x0 pull up with 4.7 k w resistor 93 x1 open 109 110 10 to 16 42 43 46 47 48 to 53 17 to 24 25 to 32 34 to 41 55 to 61 63 to 70 71 to 76 78 79 85 103 to 108 p16 p17 p41 to p47 av cc avrh p60 p61 p62 to p67 p70 to p77 p80 to p82 p90 to p97 pa 0 t o pa 7 pb0 to pb7 pc0 to pc5 p50 p51 p57 p10 to p15 connect pull-up resistor of about 1 m w to each pin
mb90220 series 22 n block diagram clock controller 5 x1 x0 rst hst md0 to md2 4 3 3 cts0 sid0 to sid2 sck0 to sck2 sod0 to sod2 sid3 sod3 sck3 tot0 to tot5 tin1 to tin5 6 5 21 atg an00 to an15 av cc avrh avrl av ss 102 p00 to p07 p10 to p17 p20 to p27 p30 to p37 p40 to p47 p50 to p57 p60 to p67 p70 to p77 p80 to p87 p90 to p97 pa0 to pa7 pb0 to pb7 pc0 to pc5 ppg0 ppg1 trg0 2 4 4 pwc0 to pwc3 pot0 to pot3 uart0 3 uart1 10-bit a/d converter 16 channels 16-bit reload timer 6 i/o ports 16-bit ppg timer 2 rom ram f 2 mc-16f cpu external bus interface dtp/external interrupt 8 24-bit timer counter icu (input capture unit) 4 ocu (output compare unit) 4 pwc timer 4 4 8 dot0 to dot7 asr0 to asr3 int0 to int7 d00 to d15 rdy hrq a00 to a23 clk hak wrh wrl rd 8 internal data bus 16 2 29 wi write-inhibit ram
23 mb90220 series n programming model accumulator user stack pointer system stack pointer processor status program counter user stack upper register system stack upper register user stack lower register system stack lower register direct page register program bank register data bank register user stack bank register system stack bank register additional bank register max.32 banks rw 7 rw 6 rw 5 rw 4 r 7 r 5 r 3 r 1 r 6 r 4 r 2 r 0 rw3 rw 2 rw 1 rw 0 rl 3 rl 2 rl 1 rl 0 000180 h + rp 10 h ilm ? i s t n z v c processor status (ps) general-purpose registers dedicated registers ah al usp ssp ps pc uspcu sspcu uspcl sspcl dpr pcb dtb usb ssb adb 8 bit 16 bit 32 bit c c r 16 bit rp lower upper msb lsb
mb90220 series 24 n memory map single chip rom area rom area rom area ff bank image rom area ff bank image internal register area internal register area write-inhibit ram write-inhibit ram ram registers registers ram peripherals peripherals peripherals internal register area write-inhibit ram registers ram : internal : external : no access ffffff h address #1 010000 h address #2 002000 h 001f00 h address #3 address #4 000380 h 000100 h 0000c0 h 000180 h internal rom and external bus external rom and external bus 000000 h type address #1 address #2 address #3 address #4 mb90223 mb90224 MB90P224A/p224b mb90w224a/w224b mb90v220 (fe0000 h ) ff0000 h fe8000 h 004000 h 004000 h 004000 h 001900 h 000f00 h 001500 h 001500 h 000d00 h 001300 h
25 mb90220 series n i/o map (continued) address register register name access resouce name initial value 000000 h *3 port 0 data register pdr0 r/w port 0 xxxxxxxx 000001 h *3 port 1 data register pdr1 r/w port 1 xxxxxxxx 000002 h *3 port 2 data register pdr2 r/w port 2 xxxxxxxx 000003 h *3 port 3 data register pdr3 r/w port 3 xxxxxxxx 000004 h *3 port 4 data register pdr4 r/w port 4 xxxxxxxx 000005 h *3 port 5 data register pdr5 r/w port 5 xxxxxxxx 000006 h port 6 data register pdr6 r/w port 6 11111111 000007 h port 7 data register pdr7 r port 7 xxxxxxxx 000008 h port 8 data register pdr8 r/w port 8 xxxxxxxx 000009 h port 9 data register pdr9 r/w port 9 11111111 00000a h port a data register pdra r/w port a xxxxxxxx 00000b h port b data register pdrb r/w port b xxxxxxxx 00000c h port c data register pdrc r/w port c CC xxxxxx 00000d h to 0f h (reserved area) *1 000010 h *3 port 0 data direction register ddr0 r/w port 0 00000000 000011 h *3 port 1 data direction register ddr1 r/w port 1 00000000 000012 h *3 port 2 data direction register ddr2 r/w port 2 00000000 000013 h *3 port 3 data direction register ddr3 r/w port 3 00000000 000014 h *3 port 4 data direction register ddr4 r/w port 4 00000000 000015 h *3 port 5 data direction register ddr5 r/w port 5 00000000 000016 h port 6 analog input enable register ader0 r/w port 6 11111111 000017 h port 7 data direction register ddr7 r/w port 7 1 1111111 000018 h port 8 data direction register ddr8 r/w port 8 0 0000000 000019 h port 9 analog input enable register ader1 r/w port 9 11111111 00001a h port a data direction register ddra r/w port a 00000000 00001b h port b data direction register ddrb r/w port b 00000000 00001c h port c data direction register ddrc r/w port c CC 000000 00001d h to 1f h (reserved area) *1 000020 h mode control register 0 umc0 r/w uart 0 (ch.0) 00000100 000021 h status register 0 usr0 r/w 00010000 000022 h input data register 0 /output data register 0 uidr0 /uodr0 r/w xxxxxxxx
mb90220 series 26 (continued) address register register name access resouce name initial value 000023 h rate and data register 0 urd0 r/w uart0 (ch.0) 0 000000x 000024 h mode control register 1 umc1 r/w uart0 (ch.1) 00000100 000025 h status register 1 usr1 r/w 00010000 000026 h input data register 1 /output data register 1 uidr1 /uodr1 r/w xxxxxxxx 000027 h rate and data register 1 urd1 r/w 0 000000x 000028 h mode control register 2 umc2 r/w uart0 (ch.2) 00000100 000029 h status register 2 usr2 r/w 00010000 00002a h input data register 2 /output data register 2 uidr2 /uodr2 r/w xxxxxxxx 00002b h rate and data register 2 urd2 r/w 0 000000x 00002c h uart cts control register uccr r/w uart0 (ch.0) C CC000CC 00002d h (reserved area) *1 00002e h mode register smr r/w uart1 00000000 00002f h control register scr r/w 00000100 000030 h input data register /output data register sidr /sodr r/w xxxxxxxx 000031 h status register ssr r/w 00001C00 000032 h a/d channel setting register adch r/w 10-bit a/d converter 00000000 000033 h a/d mode register admd r/w CCCx0000 000034 h a/d control status register adcs r/w 0000CC00 000035 h (reserved area) *1 000036 h a/d data register adcd r 10-bit a/d converter xxxxxxxx 000037 h 000000xx 000038 h (reserved area) *1 000039 h 00003a h dtp/interrupt enable register enir r/w dtp/external interrupt 00000000 00003b h dtp/interrupt source register eirr r/w 00000000 00003c h request level setting register elvr r/w 00000000 00003d h 00000000 00003e h to 3f h (reserved area) *1 000040 h timer control status register 0 tmcsr0 r/w 16-bit reload timer 0 00000000 000041 h CCCC0000
27 mb90220 series (continued) address register register name access resouce name initial value 000042 h timer control status register 1 tmcsr1 r/w 16-bit reload timer 1 00000000 000043 h CCCC0000 000044 h timer control status register 2 tmcsr2 r/w 16-bit reload timer 2 00000000 000045 h CCCC0000 000046 h timer control status register 3 tmcsr3 r/w 16-bit reload timer 3 00000000 000047 h CCCC0000 000048 h timer control status register 4 tmcsr4 r/w 16-bit reload timer 4 00000000 000049 h CCCC0000 00004a h timer control status register 5 tmcsr5 r/w 16-bit reload timer 5 00000000 00004b h CCCC0000 00004c h ppg control status register 0 pcnt0 r/w 16-bit ppg timer 0 00000000 00004d h 00000000 00004e h ppg control status register 1 pcnt1 r/w 16-bit ppg timer 1 00000000 00004f h 00000000 000050 h pwc control status register 0 pwcsr0 r/w pwc timer 0 00000000 000051 h 00000000 000052 h pwc control status register 1 pwcsr1 r/w pwc timer 1 00000000 000053 h 00000000 000054 h pwc control status register 2 pwcsr2 r/w pwc timer 2 00000000 000055 h 00000000 000056 h pwc control status register 3 pwcsr3 r/w pwc timer 3 00000000 000057 h 00000000 000058 h icu control register 0 icc0 r/w icu (input capture unit) 00000000 000059 h (reserved area) *1 00005a h input capture control register 1 icc1 r/w icu (input capture unit) 00000000 00005b h (reserved area) *1 00005c h 00005d h 00005e h 00005f h 000060 h ocu control register 00 ccr00 r/w ocu (output compare unit) 11110000 000061 h CCCC0000
mb90220 series 28 (continued) address register register name access resouce name initial value 000062 h ocu0 control register 01 ccr01 r/w ocu (output compare unit) 11110000 000063 h CCCC0000 000064 h (reserved area) *1 000065 h 000066 h 000067 h 000068 h ocu0 control register 10 ccr10 r/w ocu (output compare unit) CCCC0000 000069 h 00000000 00006a h ocu0 control register 11 ccr11 r/w CCCC0000 00006b h 00000000 00006c h (reserved area) *1 00006d h 00006e h 00006f h 000070 h free-run timer control register tccr r/w 24-bit timer counter 11000000 000071 h CC111111 000072 h free-run timer lower-order data register tcrl r 00000000 000073 h 00000000 000074 h free-run timer upper-order data register tcrh 00000000 000075 h 00000000 000076 h (reserved area) *1 000077 h 000078 h 000079 h 00007a h pwc divider ratio control register 0 divr0 r/w pwc timer 0 CCCCCC00 00007b h reserved area *1 00007c h pwc divider ratio control register 1 divr1 r/w pwc timer 1 CCCCCC00 00007d h reserved area *1 00007e h pwc divider ratio control register 2 divr2 r/w pwc timer 2 CCCCCC00 00007f h reserved area *1 000080 h pwc divider ratio control register 3 divr3 r/w pwc timer 3 CCCCCC00 000081 h to 8d h (reserved area) *1
29 mb90220 series (continued) address register register name access resouce name initial value 00008e h wi control register wicr r/w write-inhibit ram CCCxCCCC 00008f h (reserved area) *1 000090 h to 9e h 00009f h delay interrupt source generation /release register dirr r/w delay interrupt generation module CCCCCCC0 0000a0 h standby control register stbyc r/w low power consumption 0001**** 0000a3 h address mid-order control register macr w external pin ######## 0000a4 h address higher-order control register hacr w external pin ######## 0000a5 h external pin control register epcr w external pin ##0C0#00 0000a8 h watchdog timer control register wdtc r/w watchdog timer xxxxxxxx 0000a9 h timebase timer control register tbtc r/w timebase timer CCC00000 0000b0 h interrupt control register 00 icr00 r/w interrupt controller 00000111 0000b1 h interrupt control register 01 icr01 r/w 00000111 0000b2 h interrupt control register 02 icr02 r/w 00000111 0000b3 h interrupt control register 03 icr03 r/w 00000111 0000b4 h interrupt control register 04 icr04 r/w 00000111 0000b5 h interrupt control register 05 icr05 r/w 00000111 0000b6 h interrupt control register 06 icr06 r/w 00000111 0000b7 h interrupt control register 07 icr07 r/w 00000111 0000b8 h interrupt control register 08 icr08 r/w 00000111 0000b9 h interrupt control register 09 icr09 r/w 00000111 0000ba h interrupt control register 10 icr10 r/w 00000111 0000bb h interrupt control register 11 icr11 r/w 00000111 0000bc h interrupt control register 12 icr12 r/w 00000111 0000bd h interrupt control register 13 icr13 r/w 00000111 0000be h interrupt control register 14 icr14 r/w 00000111 0000bf h interrupt control register 15 icr15 r/w 00000111 0000c0 h to ff h (external area) *2 001f00 h pwc data buffer register 0 pwcr0 r/w pwc timer 0 00000000 001f01 h 00000000
mb90220 series 30 (continued) address register register name access resouce name initial value 001f02 h pwc data buffer register 1 pwcr1 r/w pwc timer 1 00000000 001f03 h 00000000 001f04 h pwc data buffer register 2 pwcr2 r/w pwc timer 2 00000000 001f05 h 00000000 001f06 h pwc data buffer register 3 pwcr3 r/w pwc timer 3 00000000 001f07 h 00000000 001f08 h to 1f0f h (reserved area) *1 001f10 h ocu compare lower-order data register 00 cpr00l r/w output compare 00 00000000 001f11 h 00000000 001f12 h ocu compare higher-order data register 00 cpr00 00000000 001f13 h 00000000 001f14 h ocu compare lower-order data register 01 cpr01l r/w output compare 01 00000000 001f15 h 00000000 001f16 h ocu compare higher-order data register 01 cpr01 00000000 001f17 h 00000000 001f18 h ocu compare lower-order data register 02 cpr02l r/w output compare 02 00000000 001f19 h 00000000 001f1a h ocu compare higher-order data register 02 cpr02 00000000 001f1b h 00000000 001f1c h ocu compare lower-order data register 03 cpr03l r/w output compare 03 00000000 001f1d h 00000000 001f1e h ocu compare higher-order data register 03 cpr03 00000000 001f1f h 00000000 001f20 h ocu compare lower-order data register 04 cpr04l r/w output compare 10 00000000 001f21 h 00000000 001f22 h ocu compare higher-order data register 04 cpr04 00000000 001f23 h 00000000 001f24 h ocu compare lower-order data register 05 cpr05l r/w output compare 11 00000000 001f25 h 00000000 001f26 h ocu compare higher-order data register 05 cpr05 00000000 001f27 h 00000000
31 mb90220 series (continued) address register register name access resouce name initial value 001f28 h ocu compare lower-order data register 06 cpr06l r/w output compare 12 00000000 001f29 h 00000000 001f2a h ocu compare higher-order data register 06 cpr06 00000000 001f2b h 00000000 001f2c h ocu compare lower-order data register 07 cpr07l r/w output compare 13 00000000 001f2d h 00000000 001f2e h ocu compare higher-order data register 07 cpr07 00000000 001f2f h 00000000 001f30 h 16-bit timer register 0 tmr0 r 16-bit reload timer 0 xxxxxxxx 001f31 h xxxxxxxx 001f32 h 16-bit reload register 0 tmrlr0 w xxxxxxxx 001f33 h xxxxxxxx 001f34 h 16-bit timer register 1 tmr1 r 16-bit reload timer 1 xxxxxxxx 001f35 h xxxxxxxx 001f36 h 16-bit timer reload register 1 tmrlr1 w xxxxxxxx 001f37 h xxxxxxxx 001f38 h 16-bit timer register 2 tmr2 r 16-bit reload timer 2 xxxxxxxx 001f39 h xxxxxxxx 001f3a h 16-bit timer reload register 2 tmrlr2 w xxxxxxxx 001f3b h xxxxxxxx 001f3c h 16-bit timer register 3 tmr3 r 16-bit reload timer 3 xxxxxxxx 001f3d h xxxxxxxx 001f3e h 16-bit timer reload register 3 tmrlr3 w xxxxxxxx 001f3f h xxxxxxxx 001f40 h 16-bit timer register 4 tmr4 r 16-bit reload timer 4 xxxxxxxx 001f41 h xxxxxxxx 001f42 h 16-bit timer reload register 4 tmrlr4 w xxxxxxxx 001f43 h xxxxxxxx 001f44 h 16-bit timer register 5 tmr5 r 16-bit reload timer 0 xxxxxxxx 001f45 h xxxxxxxx 001f46 h 16-bit timer reload register 5 tmrlr5 w xxxxxxxx 001f47 h xxxxxxxx
mb90220 series 32 (continued) initial value 0: the initial value of this bit is 0. 1: the initial value of this bit is 1. x: the initial value of this bit is undefined. C: this bit is not used. the initial value is undefined. *: the initial value of this bit varies with the reset source. #: the initial value of this bit varies with the operation mode. *1: access prohibited *2: only this area is open to external access in the area below address 0000ff h (inclusive). all addresses which are not described in the table are reserved areas, and accesses to these areas are handled in the same manner as for internal areas. the access signal for the external bus is not generated. *3: when an external bus is enable mode, never access to resisters which are not used as general ports in areas address 000000 h to 000005 h or 000010 h to 000015 h . address register register name access resouce name initial value 001f48 h ppg cycle setting register 0 pcsr0 w 16-bit ppg timer 0 xxxxxxxx 001f49 h xxxxxxxx 001f4a h ppg duty setting register 0 pdut0 w xxxxxxxx 001f4b h xxxxxxxx 001f4c h ppg cycle setting register 1 pcsr1 w 16-bit ppg timer 1 xxxxxxxx 001f4d h xxxxxxxx 001f4e h ppg duty setting register 1 pdut1 w xxxxxxxx 001f4f h xxxxxxxx 001f50 h icu lower-order data register 0 icrl0 r input capture 0 xxxxxxxx 001f51 h xxxxxxxx 001f52 h icu higher-order data register 0 icrh0 r xxxxxxxx 001f53 h 00000000 001f54 h icu lower-order data register 1 icrl1 r input capture 1 xxxxxxxx 001f55 h xxxxxxxx 001f56 h icu higher-order data register 1 icrh1 r xxxxxxxx 001f57 h 00000000 001f58 h icu lower-order data register 2 icrl2 r input capture 2 xxxxxxxx 001f59 h xxxxxxxx 001f5a h icu higher-order data register 2 icrh2 r xxxxxxxx 001f5b h 00000000 001f5c h icu lower-order data register 3 icrl3 r input capture 3 xxxxxxxx 001f5d h xxxxxxxx 001f5e h icu higher-order data register 3 icrh3 r xxxxxxxx 001f5f h 00000000 001f60 h to 1fff h (reserved area) *1
33 mb90220 series n interrupt sources and interrupt vectors/interrupt control registers (continued) interrupt source ei 2 os support interrupt vector interrupt control register no. address icr address reset #08 08 h ffffdc h int9 instruction #09 09 h ffffd8 h exception #10 0a h ffffd4 h external interrupt #0 #11 0b h ffffd0 h icr00 0000b0 h external interrupt #1 #12 0c h ffffcc h external interrupt #2 #13 0d h ffffc8 h icr01 0000b1 h input capture 0 #14 0e h ffffc4 h pwc0 count completed/overflow #15 0f h ffffc0 h icr02 0000b2 h pwc1 count completed/overflow/input capture 1 #16 10 h ffffbc h pwc2 count completed/overflow/input capture 2 #17 11 h ffffb8 h icr03 0000b3 h pwc3 count completed/overflow/input capture 3 #18 12 h ffffb4 h 24-bit timer, overflow #19 13 h ffffb0 h icr04 0000b4 h 24-bit timer, intermediate bit/timebase timer, interval interrupt #20 14 h ffffac h compare 0 #21 15 h ffffa8 h icr05 0000b5 h compare 1 #22 16 h ffffa4 h compare 2 #23 17 h ffffa0 h icr06 0000b6 h compare 3 #24 18 h ffff9c h compare 4/6 #25 19 h ffff98 h icr07 0000b7 h compare 5/7 #26 1a h ffff94 h 16-bit timer 0/1/2, overflow/ppg0 #27 1b h ffff90 h icr08 0000b8 h 16-bit timer 3/4/5, overflow/ppg1 #28 1c h ffff8c h 10-bit a/d converter count completed #29 1d h ffff88 h icr09 0000b9 h uart1 transmission completed #31 1f h ffff80 h icr10 0000ba h uart1 reception completed #32 20 h ffff7c h uart0 (ch.1) transmission completed #33 21 h ffff78 h icr11 0000bb h uart0 (ch.2) transmission completed #34 22 h ffff74 h uart0 (ch.1) reception completed #35 23 h ffff70 h icr12 0000bc h uart0 (ch.2) reception completed #36 24 h ffff6c h uart0 (ch.0) transmission completed #37 25 h ffff68 h icr13 0000bd h
mb90220 series 34 (continued) : ei 2 os is supported (with stop request). : ei 2 os is supported (without stop request). : ei 2 os is supported; however, since two interrupt sources are allocated to a single icr, in case ei 2 os is used for one of the two, ei 2 os and ordinary interrupt are not both available for the other (with stop request). : ei 2 os is supported; however, since two interrupt sources are allocated to a single icr, in case ei 2 os is used for one of the two, ei 2 os and ordinary interrupt are not both available for the other (without stop request). : ei 2 os is not supported. note: since the interrupt sources having interrupt vector nos. 15 to 18, 20, and 25 to 28 are ored, respectively, select them by means of the interrupt enable bits of each resource. if ei 2 os is used with the above-mentioned interrupt sources ored with the interrupt vector nos. 15 to 18, 20, and 25 to 28, be sure to activate one of the interrupt sources. also in this case, a request flag in the same series as the one interrupt source is likely to be cleared automatically by ei 2 os. assume for example that an interrupt for compare 4 of the interrupt vector no. 25 is activated at this time by icr07, so that the compare 6 is disabled. if ei 2 os is activated at this time by icr07, so that the compare 6 interrupt takes place during generation of or simultaneously with the compare 4 interrupt, not only the interrupt flag for the compare 4 but also that for the compare 6 will be automatically cleared after ei 2 os is automatically transferred due to the compare 4 interrupt. interrupt source ei 2 os support interrupt vector interrupt control register no. address icr address uart0 (ch.0) reception completed #39 27 h ffff60 h icr14 0000be h delay interrupt generation module #42 2a h ffff54 h icr15 0000bf h stack fault #255 ff h fffc00 h
35 mb90220 series n peripheral resources 1. parallel ports the mb90220 series has 86 i/o pins and 16 open-drain i/o pins. (1) register configuration register name address register name address note: there are no register bits for bits 7 and 6 of port c. note: there are no register bits for bits 7 and 6 of port c. register name address register name address register name address register name address 000001 h 000003 h 000005 h 000007 h 000009 h 00000b h pd x 7 pd x 6 pd x 5 pd x 4 pd x 3 pd x 2 pd x 1 pd x 0 pd x 7 pd x 6 pd x 5 pd x 4 pd x 3 pd x 2 pd x 1 pd x 0 pdr7 only: pdr0 pdr2 pdr4 pdr6 pdr8 pdra pdrc 000000 h 000002 h 000004 h 000006 h 000008 h 00000a h 00000c h ddr1 ddr3 ddr5 ddr7 ddrb 000011 h 000013 h 000015 h 000017 h 00001b h ddr0 ddr2 ddr4 ddr8 ddra ddrc 000010 h 000012 h 000014 h 000018 h 00001a h 00001c h dd x 7 dd x 6 dd x 5 dd x 4 dd x 3 dd x 2 dd x 1 dd x 0 ader0 000016 h ae07 ae06 ae05 ae04 ae03 ae02 ae01 ae00 ader1 000019 h ae15 ae14 ae13 ae12 ae11 ae10 ae09 ae08 pdr1 pdr3 pdr5 pdr7 pdr9 pdrb (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r) (r) (r) (r) (r) (r) (r) (r) xxxxxxxx b (pdr9 only: 11111111) (pdr6 only: 11111111) (pdr7 only: 11111111) xxxxxxxx b bit7 bit6 bit5 bit 4 bit3 bit2 bit1 bit0 bit7 bit6 bit5 bit 4 bit3 bit2 bit1 bit0 00000000 b bit7 bit6 bit5 bit 4 bit3 bit2 bit1 bit0 11111111 b bit7 bit6 bit5 bit 4 bit3 bit2 bit1 bit0 11111111 b initial value initial value initial value initial value dd x 7 dd x 6 dd x 5 dd x 4 dd x 3 dd x 2 dd x 1 dd x 0 bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 00000000 b initial value initial value ? port 0 to c data register (pdr0 to pdrc) ? port 0 to c data register (pdr0 to pdrc) ? port 6, 9 analog input enable register (ader0, ader1)
mb90220 series 36 (2) block diagram internal data bus data register read data register write direction register write direction register read data register direction register pin internal data bus internal data bus data register read data register write ader register write ader register read data register ader pin rmw (read-modify-write instruction) data register read direction register write direction register read direction register pin port 7 4 4 4 dot0 to dot3 (ocu) note: port 7 is input port. this pin also usable as i/o port for ocu internal function. ? i/o port (port 0 to 5, 8, and a to c) ? i/o ports with an open-drain output (port 6, and 9) ? i/o port (port 7)
37 mb90220 series 2. 16-bit reload timer (with event count function) the 16-bit reload timer 1 consists of a 16-bit down counter, a 16-bit reload register, an input pin (tin), an output pin (tot), and a control register. the input clock can be selected from among three internal clocks and one external clock. at the output pin (tot), the pulses in the toggled output waveform are output in the reload mode; the rectangular pulses indicating that the timer is counting are in the single-shot mode. the input pin (tin) can be used for event input in the event count mode, and for trigger input or gate input in the internal clock mode. the mb90220 series has six channels for this timer. (1) register configuration 000041 h 000043 h 000045 h 000047 h 000049 h 00004b h csl1 csl0 mod2 bit15 bit14 bit13 bit12 bit11 bit10 bit9 mod1 bit8 (? (r/w) (? (? (? (r/w) (r/w) (r/w) mod0 oute outl reld inte uf cnte bit7 bit6 bit5 bit4 bit3 bit2 bit1 trg bit0 000040 h 000042 h 000044 h 000046 h 000048 h 00004a h 001f31 h 001f35 h 001f39 h 001f3d h 001f41 h 001f45 h 001f30 h 001f34 h 001f38 h 001f3c h 001f40 h 001f44 h 001f33 h 001f37 h 001f3b h 001f3f h 001f43 h 001f47 h (r) (r) (r) (r) (r) (r) (r) (r) (r) (r) (r) (r) (r) (r) (r) (r) (w) (w) (w) (w) (w) (w) (w) (w) bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 tmcsr0 tmcsr1 tmcsr2 tmcsr3 tmcsr4 tmcsr5 - - - - 0000 b 00000000 b tmcsr0 tmcsr1 tmcsr2 tmcsr3 tmcsr4 tmcsr5 tmr0 tmr1 tmr2 tmr3 tmr4 tmr5 xxxxxxxx b tmr0 tmr1 tmr2 tmr3 tmr4 tmr5 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 xxxxxxxx b bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 xxxxxxxx b tmrlr0 tmrlr1 tmrlr2 tmrlr3 tmrlr4 tmrlr5 register name address register name address register name address register name address register name address initial value initial value (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) initial value initial value initial value ? timer control status register 0 to 5 (tmcsr0 to tmcsr5) ? 16-bit timer register 0 to 5 (tmr0 to tmr5) ? 16-bit timer reload register 0 to 5 (tmrlr0 to tmrlr5)
mb90220 series 38 (2) block diagram (w) (w) (w) (w) (w) (w) (w) (w) 001f32 h 001f36 h 001f3a h 001f3e h 001f42 h 001f46 h bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 xxxxxxxx b tmrlr0 tmrlr1 tmrlr2 tmrlr3 tmrlr4 tmrlr5 register name address initial value 16-bit reload register 16-bit down counter uf reload oute reld outl inte uf ei 2 os clear cnte trg irq port (tin) port (tot) 2 retrigger 3 mod2 mod1 mod0 prescaler clear internal clock 3 exck csl1 csl0 gate 2 clock selector 2 16 8 16 fff 2 1 2 3 2 5 out ctl. in ctl. internal data bus a/d (timer ch3 output) uart0 (timer ch5 output) uart1 (timer ch4 output)
39 mb90220 series 3. uart0 uart0 is a serial i/o port for synchronous or asynchronous communication with external resources. it has the following features: ? full duplex double buffer ? clk synchronous and clk asynchronous data transfers capable ? multiprocessor mode support (mode 2) ? built-in dedicated baud-rate generator (12 rates) ? arbitrary baud-rate setting from external clock input or internal timer ? variable data length (7 to 9 bits (without parity bit); 6 to 8 bits (with parity bit)) ? error detection function (framing, overrun, parity) ? interrupt function (two sources for transmission and reception) ? transfer in nrz format the mb90220 has three of these modules on chip. (1) register configuration 000020 h 000024 h 000028 h pen sbl mc1 mc0 smde rfc scke bit7 bit6 bit5 bit4 bit3 bit2 bit1 soe bit0 000022 h 000026 h 00002a h d7 d6 d5 d4 d3 d2 d1 d0 bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 000021 h 000025 h 000029 h (r) (r) (r) (r) (r) (r/w) (r/w) (r) rdrf orfe pe tdre rie tie rbf tbf 000023 h 000027 h 00002b h bch rc3 rc2 rc1 rc0 bch0 p d8 umc0 umc1 umc2 usr0 usr1 usr2 00000100 b 00001000 b uidr0/uodr0 uidr1/uodr1 uidr2/uodr2 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 xxxxxxxx b urd0 urd1 urd2 bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 0000000x b register name address serial mode control register register name address register name address register name address initial value initial value initial value initial value (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) ? mode control register 0 to 2 (umc0 to umc2) ? status register 0 to 2 (usr0 to usr2) ? input data register 0 to 2 (uidr0 to uidr2)/ouput data register 0 to 2 (uodr0 to uodr2) ? rate and data register 0 to 2 (urd0 to urd2) 00002c h (? (? (? (r/w) (r/w) (r/w) (? (? cte csp ctse uccr bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 - - - 000 - - b register name address initial value ? uart cts control register (uccr)
mb90220 series 40 (2) block diagram control bus dedicated baud rate clock 16-bit reload timer 5 (internally connected) external clock clock selector receiving clock transmitting clock receiving interrupt (to cpu) sck transmission interrupt (to cpu) transmission controller transmission start circuit transmitted bit counter transmission parity counter sod transmitting shifter uodr start of transmission receiving controller start bit detector received bit counter received parity counter receiving shifter end of reception uidr received status determination circuit signal indicating occurrence of receiving error for ei 2 os (to cpu) internal data bus umc register usr register pen sbl mc1 mc0 smde rfc scke soe rdrf orfe pe tdre rie tie rbf tbf urd register bch rc3 rc2 rc1 rc0 bch p d8 control bus sid
41 mb90220 series 4. uart1 the uart1 is a serial i/o port for asynchronous communications (start-stop synchronization) or clk synchronized communications. it has the following features: ? full-duplex double buffering ? permits asynchronous (start-stop synchronization) and clk synchronous communications ? multiprocessor mode support ? built-in dedicated baud rate generator asynchronous: 9615, 31250, 4808, 2404, and 1202 bps clk synchronization: 1 m, 500 k, 250 k bps ? arbitray baud-rate setting from external clock input or internal timer ? error detection function (parity errors, framing errors, and overrun errors) ? transfer in format nrz ? extended supports intelligent i/o service (1) register configuration bit15 bit14 bit13 bit12 bit11 bit10 bit9 pen p sbl cl a/d rec rxe txe bit8 00002f h scr 00000100 b bit7 bit6 bit5 bit4 bit3 bit2 bit1 md1 md0 cs2 cs1 cs0 bch scke soe bit0 00002e h smr 00000000 b d7 d6 d5 d4 d3 d2 d1 d0 000030 h sidr xxxxxxxx b d7 d6 d5 d4 d3 d2 d1 d0 000030 h sodr xxxxxxxx b pe ore fre rdrf tdre rie tie 000031 h ssr 00001-00 b bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 register name address register name address register name address register name address register name address initial value initial value initial value initial value (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r) (r/w) (r/w) (w) (w) (w) (w) (w) (w) (w) (w) (r) (r) (r) (r) (r) (r) (r) (r) (r) (r) (r) (r) (r) (r/w) (r/w) ? mode register (smr) ? scr (control register) ? input data register (sidr)/serial output data register (sodr) ? ssr (status register)
mb90220 series 42 (2) block diagram control signals dedicated baud rate generator external clock clock selector receiving clock transmitting clock receiving interrupt (to cpu) sck3 transmission interrupt (to cpu) transmission controller transmission start circuit transmitted bit counter transmission parity counter sod3 transmitting shifter sodr start of transmission receiving controller start bit detector received bit counter received parity counter receiving shifter end of reception sidr received status determination circuit signal indicating occurrence of receiving error for ei 2 os (to cpu) internal data bus smr register scr register md1 md0 cs2 cs1 cs0 bch scke soe pen p sbl cl a/d rec rxe txe ssr register pe ore fre rdrf tdre rie tie control signals sid3 16-bit reload timer 4 (internally connected)
43 mb90220 series 5. 10-bit a/d converter the 10-bit a/d converter converts analog input voltage into a digital value. the features of this module are described below: ? conversion time: 6.125 m s/channel (min.) (with machine clock running at 16 mhz) ? uses rc-type sequential comparison and conversion method with built-in sample and hold circuit ? 10-bit resolution ? analog input can be selected by software from among 16 channels single-conversion mode: selects and converts one channel. scan conversion mode: converts several consecutive channels (up to 16 can be programmed). one-shot mode: converts the specified channel once and terminates. continuous conversion mode: repeatedly converts the specified channel. stop conversion mode: pauses after converting one channel and waits until the next startup (permits synchronization of start of conversion). ? when a/d conversion is completed, an a/d conversion complete interrupt request can be issued to the cpu. because the generation of this interrupt can be used to start up the ei 2 os and transfer the a/d conversion results to memory, this function is suitable for continuous processing. ? startup triggers can be selected from among software, an external trigger (falling edge), and a timer (rising edge). (1) register configuration bit7 bit6 bit5 bit4 bit3 bit2 bit1 ans3 ans2 ans1 ans0 ane3 ane2 ane1 ane0 bit0 000032 h adch 00000000 b bit15 bit14 bit13 bit12 bit11 bit10 bit9 mod1 mod0 sts1 sts0 bit8 (r/w) (? (r/w) (? (? (w) (r/w) (r/w) busy int inte paus strt (? (r/w) (w) (r/w) (r/w) (r/w) (? (r/w) d7 d6 d5 d4 d3 d2 d1 d0 000033 h admd - - - x0000 b bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 000034 h adcs 0000 - - 00 b xxxxxxxx b 000036 h adcd bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 register name address this register specfies the a/d converter conversion channel. this register specfies the a/d converter operation mode and the startup source. this register is the a/d converter control and status register. note: program ??to bit 12 when write. read value is indeterminated. this register stores the a/d converter conversion data. register name address register name address register name address initial value initial value initial value initial value (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) reserved reserved (r) (r) (r) (r) (r) (r) (r) (r) ? a/d channel setting register (adch) ? a/d mode register (admd) ? a/d control status register (adcs) ? a/d data register (adcd)
mb90220 series 44 (2) block diagram d9 d8 000037 h adcd bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 000000xx b register name address initial value (r) (r) (r) (r) (r) (r) (r) (r) mpx an0 an1 an2 an3 an4 an5 an6 an7 an8 an9 an10 an11 an12 an13 an14 an15 comparator sample and hold circuit avcc avrh/avrl av ss d/a converter sequential comparison register a/d data register adcd adch admd adcs a/d channel setting register a/d mode register a/d control status register operation clock prescaler f timer (16-bit reload timer 3 output) timer startup machine clock atg trigger startup input circuit decoder internal data bus
45 mb90220 series 6. pwc (pulse width count) timer the pwc (pulse width count) timer is a 16-bit multifunction up-count timer with an input-signal pulse-width count function and a reload timer function. the hardware configuration of this module is a 16-bit up-count timer, an input pulse divider with divide ratio control register, four count input pins, and a 16-bit control register. using these components, the pwc timer provides the following features: ? timer functions: an interrupt request can be generated at set time intervals. pulse signals synchronized with the timer cycle can be output. the reference internal clock can be selected from among three internal clocks. ? pulse-width count functions: the time between arbitrary pulse input events can be counted. the reference internal clock can be selected from among three internal clocks. various count modes: h pulse width ( - to )/l pulse width ( to - ) rising-edge cycle ( - to - /falling-edge cycle ( to ) count between edges ( - or to or - ) cycle count can be performed by 2 2n division (n = 1, 2, 3, 4) of the input pulse, with an 8 bit input divider. an interrupt request can be generated once counting has been performed. the number of times counting is to be performed (once or subsequently) can be selected. the mb90220 series has four channels for this module. (1) register configuration bit15 bit14 bit13 bit12 bit11 bit10 bit9 strt stop edir edie ovir ovie err pout bit8 000051 h 000053 h 000055 h 000057 h bit7 bit6 bit5 bit4 bit3 bit2 bit1 cks1 cks0 pis1 pis0 s/c mod1 mod1 mod0 bit0 000050 h 000052 h 000054 h 000056 h 001f01 h 001f03 h 001f05 h 001f07 h 001f00 h 001f02 h 001f04 h 001f06 h pwcsr0 pwcsr1 pwcsr2 pwcsr3 00000000 b pwcsr0 pwcsr1 pwcsr2 pwcsr3 00000000 b pwcr0 pwcr1 pwcr2 pwcr3 00000000 b pwcr0 pwcr1 pwcr2 pwcr3 00000000 b bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 register name address register name address register name address register name address (r/w) (r/w) (r) (r/w) (r/w) (r/w) (r) (r/w) initial value initial value initial value initial value bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) ? pwc control status register 0 to 3 (pwcsr0 to pwcsr3) ? pwc data buffer register 0 to 3 (pwcr0 to pwcr3)
mb90220 series 46 (2) block diagram 00007a h 00007c h 00007e h 000080 h (r/w) (r/w) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 divr0 divr1 divr2 divr3 - - - - - - 00 b register name address initial value mod1 mod0 (? (? (? (? (? (? ? pwc division ratio control register 0 to 3 (divr0 to divr3) clock divider internal clock (machine clock/4) 2 3 2 2 cks 1 cks 0 divider clear pis 1 pis 0 pwc 0 pwc 1 pwc 2 pwc 3 * f.f. pot overflow divr 2 15 pwcsr overflow interrupt request count end interrupt request count end edge count start edge edge detector start edge select end edge select err pis 1 pis 0 cks 1 cks 0 divider selection 8-bit divider division on/off controller 16-bit up-count timer 16 error detector pwcr 16 16 16 timer clear count enable clock overflow data transfer reload err pwcr read internal data bus flag set, etc. write enable control bit output *: in the mb90220 series, only the module input pwc 0 of each channel is connected to the respective external pins. channel pot pin pwc ch. 0 pwc ch. 1 pwc ch. 2 pwc ch. 3 pa 1/pwc 0/pot 0 pa 2/pwc 1/pot 1/asr 1 pa 3/pwc 2/pot 2/asr 2 pa 4/pwc 3pot 3/asr 3
47 mb90220 series 7. dtp/external interrupts dtp (data transfer peripheral) is located between external peripherals and the f 2 mc-16f cpu. it receives a dma request or an interrupt request generated by the external peripherals and reports it to the f 2 mc-16f cpu to activate the extended intelligent i/o service or interrupt handler. the user can select two request levels of h and l for extended intelligent i/o service or, and four request levels of h, l, rising edge and falling edge for external interrupt requests. in mb90220, only parts corresponding to int2 to int0 are usable as external interrupt/dtp request. parts corresponding to int7 to int3 cannot be used as external interrupt/dtp request, but only for edge detection at external terminals. note: int7 to int3 are not usable as dtp/external interrupts. (1) register configuration (2) block diagram bit15 bit14 bit13 bit12 bit11 bit10 bit9 er7 er6 er5 er4 er3 er2 er1 er0 bit8 00003a h bit7 bit6 bit5 bit4 bit3 bit2 bit1 en7 en6 en5 en4 en3 en2 en1 en0 bit0 00003b h lb7 la7 lb6 la6 lb5 la5 lb4 la4 00003d h 00003c h lb3 la3 lb2 la2 lb1 la1 lb0 la0 enir 00000000 b 00000000 b eirr bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 00000000 b elvr elvr bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 00000000 b register name address register name address register name address register name address initial value initial value initial value initial value (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) ? dtp/interrupt enable register (enir) ? request level setting register (elvr) ? dtp/interrupt source register (eirr) interrupt/dtp enable register 4 gate 4 source f/f edge detector 8 interrupt/dtp source register 4 request level setting register 8 int internal data bus
mb90220 series 48 8. 24-bit timer counter the 24-bit timer counter consists of a 24-bit up-counter, an 8-bit output buffer register, and a control register. the count value output by this timer counter is used to generate the base time used for input capture and output compare. the interrupt functions provided are timer overflow interrupts and timer intermediate bit interrupts. the intermediate bit interrupt permits four time settings. the 24-bit timer counter value is cleared to all zeroes by a reset. (1) register configuration tccr 000071 h bit15 bit14 bit13 bit12 bit11 bit10 bit9 pr0 bit8 (r/w) (? (r/w) (? (w) (w) (r/w) (r/w) bit7 bit6 bit5 bit4 bit3 bit2 bit1 clr2 clr ivf ivfe tim time tis1 tis0 bit0 (r/w) (w) (r/w) (w) (r/w) (r/w) (r/w) (r/w) tcrl 000072 h 000073 h 00000000 b tcrl bit15 bit0 tcrh 000074 h 000075 h 00000000 b tcrh bit15 bit0 bit8 bit7 tccr 000070 h - - 111111 b 11000000 b access r access r register name address register name address register name address register name address initial value initial value initial value initial value reserved reserved reserved reserved reserved ? free-run timer control register (tccr) ? free-run timer low-order data register (tcrl) ? free-run timer high-order data register (tcrh)
49 mb90220 series (2) block diagram 2 internal basic clock f /3 f /4 2 timer counter clocks ck0 pr0 2 clear bit clr clr2 2 ck0 ck1 2 lower-order 16-bit counter 4 clr/clr2 higher-order 8-bit counter carry 2 8 16 ck0, ck1 timer counter bit output t23 to t16 t0 to t15 output buffer 8 16 23rd bit 16 16 2 4 tis1 tis0 intermediate bit interrupt cycle setting 10th bit 11th bit 12th bit 13th bit interrupt enable interrupt flag ivf ivfe tim time intermediate bit interrupt request overflow interrupt request tim ivf internal data bus ck1 clr (prescaler clear) clr2 (prescaler clear, 24-bit timer counter stop bit) ?
mb90220 series 50 9. ocu (output compare unit) the ocu (output compare unit) consists of a 24-bit output compare register, a comparator, and a control register. the match detection signal is output when the contents of the output compare register match the contents of the 24-bit timer counter. this match detection signal can be used to change the output value of the corresponding pin, or can be used to generate an interrupt. one block consists of four output compare units, and the four output compare registers use one comparator to perform time division comparisons. (1) register configuration bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 000061 h 000063 h (? (? (? (? (r/w) (r/w) (r/w) (r/w) (? (? (? (? (r/w) (r/w) (r/w) (r/w) md3md2md1md0 000060 h 000062 h sel3 sel2 sel1 sel0 cpe3 cpe2 cpe1 cpe0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 000069 h 00006b h ice3 ice2 ice1 ice0 ic3 ic2 ic1 ic0 000068 h 00006a h dot3 dot2 dot1 dot0 001f11 h 001f15 h 001f19 h 001f1d h 001f21 h 001f25 h 001f29 h 001f2d h 001f10 h 001f14 h 001f18 h 001f1c h 001f20 h 001f24 h 001f28 h 001f2c h ccr00 ccr02 ccr00 ccr02 - - - - 0000 ccr10 ccr11 11110000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 ccr10 ccr11 00000000 - - - - 0000 cpr00l cpr01l cpr02l cpr03l cpr04l cpr05l cpr06l cpr07l cpr00l cpr01l cpr02l cpr03l cpr04l cpr05l cpr06l cpr07l bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 00000000 00000000 register name address register name address register name address register name address register name address register name address initial value initial value initial value initial value initial value initial value (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) ? ocuo control register 00, 01 (ccr00, ccr01) ? ocuo control register 10, 11 (ccr10, ccr11) ? ocu compare low-order data register 00 to 07 (cpr00l to cpr07l)
51 mb90220 series 001f13 h 001f17 h 001f1b h 001f1f h 001f23 h 001f27 h 001f2b h 001f2f h 001f12 h 001f16 h 001f1a h 001f1e h 001f22 h 001f26 h 001f2a h 001f2e h cpr00 cpr01 cpr02 cpr03 cpr04 cpr05 cpr06 cpr07 cpr00 cpr01 cpr02 cpr03 cpr04 cpr05 cpr06 cpr07 bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 00000000 00000000 register name address register name address initial value initial value (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r) (r) (r) (r) (r) (r) (r) (r) ? output compare high-order data register 00 to 07 (cpr00h to cpr07h)
mb90220 series 52 (2) block diagram (continued) 24-bit timer counter internal data bus 22 t2 to t23 comparator controller 24 24 24 24 814 output latch output latch 8 14 cpr03 cpr02 cpr01 cpr00 cpr03l cpr02l cpr01l cpr00l 8 4 output compare register higher-order 8 bits output compare register lower-order 16 bits 4 match source signals ext0 to 3 8 4 4 match detection signal selection 4 sel3 sel2 sel1 sel0 cpe3 cpe2 cpe1 cpe0 match operation enable source selector clock selector output latch 4 4 dot0 to 3 md3 md2 md1 md0 dot3 dot2 dot1 dot0 dot pin data output (also serves as general-purpose port data register) port general purpose/compare dedicated switching 4 4 4 icmp0 to 3 interrupt request signals match0 to 3 interrupt enable ice0 to 3 match signal ice3 ice2 ice1 ice0 ic3 ic2 ic1 ic0 interrupt flags ic0 to 3 24-bit timer counter data t0 4 4 4 direction register data register read direction register write direction register read pin port 7 compare unit*
53 mb90220 series (continued) internal data bus timer count data 16 compare unit match 0 to 3 t1 to t23 rb15 to 0 ext 0 to 3 icomp 0 to 3 dot 0 to 3 compare 00 to 03 match 0 to 3 t1 to t23 rb15 to 0 ext 0 to 3 icomp 0 to 3 dot 0 to 3 compare 10 to 13 4 16 23 open interrupt request icomp 0 to 3 4 4 4 pin output dot 0 to 3 icomp 0, 2 pin output dot 4 to 7 or or 2 2 icomp 1, 3 icomp 4/6 icomp 5/7 interrupt request *: there are two compare units drawn as below.
mb90220 series 54 10. icu (input capture unit) this module detects either the rising edge, falling edge, or both edges of an externally input waveform and holds the value of the 24-bit timer counter at that time, while at the same time the module generates an interrupt request for the cpu. the module consists of a 24-bit input capture data register and a control register. there are four external input pins (asr0 to asr3); the operation of each input is described below. asr0 to asr3: each of these input pins has a corresponding input capture register. when the specified valid edge ( - or or - ) is detected, the register can be used to store the 24-bit timer counter value. (1) register configuration 000058 h eg3b eg3a eg2b eg2a eg1b eg1a eg0b eg0a 00005a h ire3 ire2 ire1 ire0 ir3 ir2 ir1 ir0 001f50 h 001f54 h 001f58 h 001f5c h bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 d07 d06 d05 d04 d03 d02 d01 d00 d15 d14 d13 d12 d11 d10 d09 bit15 bit14 bit13 bit12 bit11 bit10 bit9 d08 bit8 001f52 h 001f56 h 001f5a h 001f5e h d23 d22 d21 d20 d19 d18 d17 d16 icco bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 icci 00000000 b 00000000 b icrl0 icrl1 icrl2 icrl3 xxxxxxxx b 001f51 h 001f55 h 001f59 h 001f5d h icrl0 icrl1 icrl2 icrl3 xxxxxxxx b icrh0 icrh1 icrh2 icrh3 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 xxxxxxxx b 00000000 b 001f53 h 001f57 h 001f5b h 001f5f h icrh0 icrh1 icrh2 icrh3 register name address register name address register name address register name address register name address register name address (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) initial value initial value initial value initial value initial value initial value (r) (r) (r) (r) (r) (r) (r) (r) (r) (r) (r) (r) (r) (r) (r) (r) (r) (r) (r) (r) (r) (r) (r) (r) (r) (r) (r) (r) (r) (r) (r) (r) ? icu control register 0 (icc0) ? icu control register 1 (icc1) ? icu low-order data register (icrl0 to icrl3) ? icu high-order data register (icrh0 to icrh3)
55 mb90220 series (2) block diagram 8 24-bit timer counter input t23 to t0 24 16 t23 to t16 t15 to t00 4 16 output latch ir0 ir1 ir2 ir3 interrupt request flags (icc1) 4 capture 8 eg3b eg3a eg2b eg2a eg1b eg1a eg0b eg0a 8 icrh0 icrh1 icrh2 icrh3 icrl0 icrl1 icrl2 icrl3 edge detection 0 edge detection 1 edge detection 2 edge detection 3 edge detection 0 to 3: - or or - 4 4 ire3 ire2 ire1 ire0 interrupt enable (icc1) 4 irq0 to irq3 egi0 to egi3 ego0 to ego3 asr3 asr2 asr1 asr0 edge detection polarity (icc0) 8 internal data bus
mb90220 series 56 11. 16-bit ppg timer this module can output a pulse synchronized with an external trigger or a software trigger. in addition, the cycle and duty ratio of the output pulse can be changed as desired by overwriting the two 16-bit register values. pwm function: synchronizes pulse with trigger, and permits programming of the pulse output by overwriting the register values mentioned above. this function permits use as a d/a converter with the addition of external circuits. one-shot function: detects the edge of trigger input, and permits single-pulse output. there is no trigger input for ppg1. this module consists of a 16-bit down-counter, a prescaler, a 16-bit synchronization setting register, a 16-bit duty register, a 16-bit control register, one external trigger input pin, and one ppg output pin. (1) register configuration 0004d h 0004f h cnte stgr mdse rtrg cks1 cks0 pgms bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 0004c h 0004e h egs1 egs0 iren irqf irs1 irs0 poen osel bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 001f49 h 001f4d h 001f48 h 001f4c h 001f4b h 001f4f h 001f4a h 001f4e h pcnt0 pcnt1 pcnt0 pcnt1 00000000 b 00000000 b bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 xxxxxxxx b xxxxxxxx b xxxxxxxx b xxxxxxxx b pcsp0 pcsp1 pdut0 pdut1 pdut0 pdut1 pcsp0 pcsp1 register name address register name address register name address register name address register name address register name address initial value initial value initial value initial value initial value initial value (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (w) (w) (w) (w) (w) (w) (w) (w) (w) (w) (w) (w) (w) (w) (w) (w) (w) (w) (w) (w) (w) (w) (w) (w) (w) (w) (w) (w) (w) (w) (w) (w) overwrite during operation ? overwrite during operation ? ? ppg control status register (pcnt0, pcnt1) ? ppg0, ppg1 cycle setting register (pcsp0, pcsp1) ? ppg0, ppg1 duty setting register (pdut0, pdut1)
57 mb90220 series (2) block diagram prescaler oscillation clock trg input edge detection software trigger enable irq reverse bit ppg output s q r ppg mask cmp pdut pcsr ck load 16-bit down-counter start borrow 1/1 1/4 1/16 1/64 interrupt selector
mb90220 series 58 12. watchdog timer and timebase timer functions the watchdog timer consists of a 2-bit watchdog counter using carry from an 18-bit timebase timer as the clock source, a control register, and a watchdog reset control section. the timebase timer consists of an 18-bit timer and an interval interrupt control circuit. (1) register configuration (2) block diagram 0000a8 h ponr stbr wrst erst srst wte wt1 wt0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0000a9 h ( )( )( )( r/w )( r/w )( r )( r/w )( r/w ) tbie tbof tbr tbc1 tbc0 bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 wdtc tbtc xxxxxxxx - - - xxxxx register name address register name address initial value initial value (r) (r) (r) (r) (r) (w) (w) (w) ? watchdog timer control register (wdtc) ? timebase timer control register (tbtc) tbtc tbc1 tbc0 tbr tbie tbof selector and qr s selector timebase interrupt wdtc wt1 wt0 wte ponr stbr wrst erst srst from rst bit of stbyc register rst pin from hardware standby controller from power-on signal generator wdgrst to internal reset signal generator 2-bit counter of clr watchdog reset signal generator clr 2 12 2 14 2 16 2 18 tbtres clock input timebase timer 2 14 2 16 2 17 2 18 oscillation clock internal data bus
59 mb90220 series 13. delay interruupt generation module the delayed interrupt generation module is used to generate an interrupt task switching. using this module allows an interrupt request to the f 2 mc-16f cpu to generated or cancel by software. (1) register configuration (2) block diagram 00009f h ( )( )( )( )( )( )( )( r/w ) r0 bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 dirr - - - - - - - 0 register name address initial value ? delay interrupt source generation/cancel register (dirr) internal data bus source latch delay interrupt source generation/cancel decoder
mb90220 series 60 14. write-inhibit ram the write-inhibit ram is write-protectable with the wi pin input. maintaining the l level input to the wi pin prevents a certain area of ram from being written. the wi pin has a 4-machine-cycle filter. (1) register configuration (2) write-inhibit ram areas write-inhibit ram areas: 000d00 h to 000eff h (mb90223) 001300 h to 0014ff h (mb90224/p224a/p224b/w224a/w224b) 001500 h to 0018ff h (mb90v220) (3) block diagram 00008e h ( )( )( )( r/w )( )( )( )( ) wi bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 wicr - - - x - - - - register name address initial value ? wi control register (wicr) wi 4-machine cycle smoothing circuit 4-machine cycle smoothing circuit s r q priority r q other area access write-inhibit circuit write-inhibit ram ram decoder select internal data bus l h wr s
61 mb90220 series 15. low-power consumption modes, oscillation stabilization delay time, and gear function the mb90220 series has three low-power consumption modes: the sleep mode, the stop mode, the hardware standby mode, and gear function. sleep mode is used to suspend only the cpu operation clock; the other components remain in operation. stop mode and hardware standby mode stop oscillation, minimizing the power consumption while holding data. the gear function divides the external clock frequency, which is used usually as it is, to provide a lower machine clock frequency. this function can therefore lower the overall operation speed without changing the oscillation frequency. the function can select the machine clock as a division of the frequency of crystal oscillation or external clock input by 1, 2, 4, or 16. the osc1 and osc0 bits can be used to set the oscillation stabilization delay time for wake-up from stop mode or hardware standby mode. (1) register configuration note: the initial value (*) of bit0 to bit3 is changed by reset source. 0000a0 h (w) (w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) stp slp spl rst osc1 osc0 clk1 clk0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 stbyc 0001* * * * register name address initial value ? standby control register (stbyc)
mb90220 series 62 (2) block diagram selector 2 14 2 0 selector gear divider 1/1 1/2 1/4 1/16 stbyc clk1 clk0 slp stp osc1 osc0 spl rst internal reset signal generator wdgrst to watchdog timer internal rst standby controller rst release hst start pin high impedance controller pin hi-z interrupt request or rst 2 16 2 17 2 18 clock input timebase timer 2 16 2 17 2 18 peripheral clock generator cpu clock generator peripheral clock cpu clock oscillation clock internal data bus hst pin rst pin
63 mb90220 series n electrical characteristics 1. absolute maximum ratings (v ss = av ss = 0.0 v) *1: v 1 must not exceed v cc + 0.3 v. *2: output pins: p00 to p07, p10 to p17, p20 to p27, p30 to p37, p40 to p47, p50 to p57, p70 to p77, p80 to p87, pa0 to pa7, pb0 to pb7, pc0 to pc5 *3: output pins: p00 to p07, p10 to p17, p20 to p27, p30 to p37, p40 to p47, p50 to p57, p60 to p67, p70 to p77, p80 to p87, p90 to p97, pa0 to pa7, pb0 to pb7, pc0 to pc5 warning:semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. parameter symbol pin name value unit remarks min. max. power supply voltage v cc v cc v ss C 0.3 v ss + 7.0 v program voltage v pp v pp v ss C 0.3 13.0 v MB90P224A/p224b mb90w224a/w224b analog power supply voltage av cc av cc v ss C 0.3 v cc + 0.3 v power supply voltage for a/d converter avrh avrl avrh avrl v ss C 0.3 av cc v reference voltage for a/d converter input voltage v i * 1 v ss C 0.3 v cc + 0.3 v output voltage v o * 2 v ss C 0.3 v cc + 0.3 v l level output current i ol * 3 20 ma rush current l level total output current s i ol * 3 50 ma total output current h level output current i oh * 2 C10 ma rush current h level total output current s i oh * 2 C48 ma total output current power consumption p d 650mw operating temperature t a C40 +105 c mb90223/224/p224b /w224b C40 +85 c MB90P224A/w224a storage temperature tstg C55 +150 c
mb90220 series 64 2. recommended operating condition (v ss = av ss = 0.0 v) * : excluding the temperature rise due to the heat produced. warning:recommended operating conditions are normal operating ranges for the semiconductor device. all the devices electrical characteristics are warranted when operated within these ranges. always use semiconductor devices within the recommended operating conditions. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representative beforehand. parameter symbol pin name value unit remarks min. max. power supply voltage v cc v cc 4.5 5.5 v when operating 3.0 5.5 v retains the ram state in stop mode analog power supply voltage av cc av cc 4.5 v cc + 0.3 v power supply voltage for a/d converter avrh avrh avrl av cc v reference voltage for a/d converter avrl avrl av ss avrh v clock frequency f c 10 16 mhz mb90224/p224a/w224a mb90p224b/w224b 10 12 mhz mb90223 operating temperature t a * C40 +105 c single-chip mode mb90223/224/p224b/ w224b C40 +85 c single-chip mode MB90P224A/w224a C40 +70 c external bus mode
65 mb90220 series 3. dc characteristics single-chip mode mb90223/224/p224b/w224b : (v cc = +4.5 v to +5.5 v, v ss = 0.0 v, t a = C40 c to +105 c) MB90P224A/w224a : (v cc = +4.5 v to +5.5 v, v ss = 0.0 v, t a = C40 c to +85 c) external bus mode : (v cc = +4.5 v to +5.5 v, v ss = 0.0 v, t a = C40 c to +70 c) (continued) parameter symbol pin name condition value unit remarks min. typ. max. h level input voltage v ih x0 0.7 v cc v cc + 0.3 v cmos level input v ihs * 1 0.8 v cc v cc + 0.3 v hysteresis input v ihm md0 to md2 v cc C 0.3 v cc + 0.3 v l level input voltage v il x0 v ss C 0.3 0.3 v cc v cmos level input v ils * 1 v ss C 0.3 0.2 v cc v hysteresis input v ilm md0 to md2 v ss C 0.3 v ss + 0.3 v h level output voltage v oh * 2 v cc = 4.5 v i oh = C4.0 ma v cc C 0.5 v cc v v oh1 x1 v cc = 4.5 v i oh = C2.0 ma v cc C 2.5 v cc v l level output voltage v ol * 3 v cc = 4.5 v i ol = 4.0 ma 00.4v v ol1 x1 v cc = 4.5 v i ol = 2.0 ma 0v cc C 2.5 v input leackage current i i * 1 v cc = 5.5 v 0.2 v cc < v i < 0.8 v cc 10 m a hysteresis input except pins with pull-up/pull- down resistor and rst pin i i2 x0 v cc = 5.5 v 0.2 v cc < v i2 < 0.8 v cc 20 m a pull-up resistor r pulu rst 22 50 110 k w * 4 mb90223/224 MB90P224A/ w224a md1 22 50 150 k w * 4 mb90223/224 pull-down resistor r puld md0 md2 22 50 150 k w * 4 mb90223/224 power supply voltage* 8 i cc v cc f c = 12 mhz 70* 5 100 ma mb90223 f c = 16 mhz 70* 5 100 ma mb90224 f c = 16 mhz 90* 5 125 ma MB90P224A/ p224b mb90w224a/ w224b i ccs v cc f c = 16 mhz* 9 60 ma at sleep mode i cch v cc 510 m a in stop mode t a = +25 c at hardware standby
mb90220 series 66 (continued) *1: hysteresis input pins rst , hst , p00 to p07, p10 to p17, p20 to p27, p30 to p37, p40 to p47, p50 to p57, p60 to p67, p80 to p87, p90 to p97, pa0 to pa7, pb0 to pb7, pc0 to pc5 *2: ouput pins p00 to p07, p10 to p17, p20 to p27, p30 to p37, p40 to p47, p50 to p57, p70 to p77, p80 to p87, pa0 to pa7, pb0 to pb7, pc0 to pc5 *3: output pins p00 to p07, p10 to p17, p20 to p27, p30 to p37, p40 to p47, p50 to p57, p60 to p67, p70 to p77, p80 to p87, p90 to p97, pa0 to pa7, pb0 to pb7, pc0 to pc5 *4: a list of availabilities of pull-up/pull-down resistors *5: v cc = +5.0 v, v ss = 0.0 v, t a = +25 c, f c = 16 mhz *6: the current value applies to the cpu stop mode with a/d converter inactive (v cc = av cc = avrh = +5.5 v). *7: other than v cc , v ss , av cc and av ss *8: measurement condition of power supply current; external clock pin and output pin are open. measurement condition of v cc ; see the table above mentioned. *9: f c = 12 mhz for mb90223 parameter symbol pin name condition value unit remarks min. typ. max. analog power supply voltage i a av cc f c = 16 mhz* 9 3 7ma i ah 5* 6 m a at stop mode input capacitance c in * 7 10pf pin name mb90223/224 MB90P224A/w224a mb90p224b/w224b rst availability of pull-up resistors is optionally defined. pull-up resistors available unavailable md1 pull-up resistors available unavailable unavailable md0, md2 pull-up resistors available unavailable unavailable
67 mb90220 series 4. ac characteristics (1) clock timing standards single-chip mode mb90223/224/p224b/w224b : (v cc = +4.5 to +5.5 v, v ss = 0.0 v, t a = C40 c to +105 c) MB90P224A/w224a : (v cc = +4.5 to +5.5 v, v ss = 0.0 v, t a = C40 c to +85 c) external bus mode : (v cc = +4.5 to +5.5 v, v ss = 0.0 v, t a = C40 c to +70 c) t c = 1/f c parameter symbol pin name condition value unit remarks min. typ. max. clock frequency f c x0, x1 10 16 mhz mb90224/ p224a/p224b mb90w224a/ w224b 10 12 mhz mb90223 clock cycle time t c x0, x1 62.5 100 ns mb90224/ p224a/p224b mb90w224a/ w224b 83.4 100 ns mb90223 input clock pulse width p wh p wl x0 0.4 t c 0.6 t c ns equivalent to 60% duty ratio input clock rising/falling times t cr t cf x0 8 ns t cr + t cf t cf t cr 0.7 v cc 0.3 v cc 0.7 v cc 0.7 v cc 0.3 v cc p wh p wl t c ? clock input timings when a crystal or ceramic resonator is used when an external clock is used open x0 x1 x0 x1 c 2 c 1 c 1 = c 2 = 10 pf select the optimum capacity value for the resonator ? clock conditions
mb90220 series 68 v cc [v] 5.5 4.5 016 fc [mhz] 10 12 single-chip mode (mb90224/p224b/w224b) (mb90223) (MB90P224A/w224a) external bus mode : t a = ?0 c to +105 c, fc = 10 to 16 mhz : t a = ?0 c to +105 c, fc = 10 to 12 mhz : t a = ?0 c to +85 c, fc = 10 to 16 mhz : t a = ?0 c to +70 c, fc = 10 to 16 mhz (fc = 10 to 12 mhz, only for mb90223) operation assurance range ? relationship between clock frequency and supply voltage
69 mb90220 series (2) clock output timing (external bus mode: v cc = +4.5 v to +5.5 v, v ss = 0.0 v, t a = C40 c to +70 c) t cyc = n/f c , n gear ratio (1, 2, 4, 16) (3) reset and hardware standby input standards single-chip mode mb90223/224/p224b/w224b: (v cc = +4.5 v to +5.5 v, v ss = 0.0 v, t a = C40 c to +105 c) MB90P224A/w224a : (v cc = +4.5 v to +5.5 v, v ss = 0.0 v, t a = C40 c to +85 c) external bus mode : (v cc = +4.5 v to +5.5 v, v ss = 0.0 v, t a = C40 c to +70 c) *: the machine cycle time (t cyc ) at hardware standby is set to 1/16 divided oscillation. parameter symbol pin name condition value unit remarks min. typ. max. machine cycle time t cyc clk load condition: 80 pf 62.5 1600 ns mb90224/ p224a/p224b mb90w224a/ 224b 83.4 1600 ns mb90223 clk - ? clk t chcl clk t cyc /2 C 20 t cyc /2 ns parameter symbol pin name condition value unit remarks min. typ. max. reset input time t rstl rst 5 t cyc ns hardware standby input time t hstl hst 5 t cyc ns* clk 1/2 v cc t cyc t chcl rst hst 0.2 v cc 0.2 v cc t rstl , t hstl
mb90220 series 70 (4) power on supply specifications (power-on reset) single-chip mode mb90223/224/p224b/w224b: (v cc = +4.5 v to +5.5 v, v ss = 0.0 v, t a = C40 c to +105 c) MB90P224A/w224a : (v cc = +4.5 v to +5.5 v, v ss = 0.0 v, t a = C40 c to +85 c) external bus mode : (v cc = +4.5 v to +5.5 v, v ss = 0.0 v, t a = C40 c to +70 c) * : before power supply rising, it is required to be v cc < 0.2 v. notes: ? power-on reset assumes the above values. ? whether the power-on reset is required or not, turn the power on according to these characteristics and trigger the power-on reset. ? there are internal registers (stbyc, etc.) which is initialized only by the power-on reset in the device. note: note on changing power supply even if above characteristics are not insufficient, abrupt changes in power supply voltage may cause a power- on reset. therefore, at the time of a momentary changes such as when power is turned on, rise the power smoothly as shown below. parameter symbol pin name condition value unit remarks min. typ. max. power supply rising time t r v cc 30ms* power supply cut-off time t off v cc 1ms v cc t r 4.5 v 0.2 v t off 0.2 v cc 0.2 v cc ? power-on reset main power supply voltage this rising edge should be 50 mv/ms or less subpower supply voltage vss ? changing power supply
71 mb90220 series (5) bus read timing (v cc = +4.5 v to +5.5 v, v ss = 0.0 v, t a = C40 c to +70 c) parameter symbol pin name condition value unit remarks min. max. valid address ? rd time t avrl a23 to a00 load condition: 80 pf t cyc /2 C 20 ns rd pulse width t rlrh rd t cyc C 25 ns rd ? valid data input t rldv d15 to d00 t cyc C 30 ns rd - ? data hold time t rhdx 0ns valid address ? valid data input t avdv 3 t cyc /2 C 40 ns rd - ? address valid time t rhax a23 to a00 t cyc /2 C 20 ns valid address ? clk - time t avch a23 to a00 clk t cyc /2 C 25 ns rd ? clk time t rlcl rd , clk t cyc /2 C 25 ns clk rd a23 to a00 d15 to d00 t rhdx read data 0.8 v cc 0.2 v cc 0.8 v cc 0.2 v cc 0.7 v cc 0.3 v cc 0.3 v cc 0.7 v cc 0.7 v cc 0.3 v cc 0.7 v cc 0.3 v cc t avch t rlcl t avrl t rlrh t rhax t rldv t avdv
mb90220 series 72 (6) bus write timing (v cc = +4.5 v to +5.5 v, v ss = 0.0 v, t a = C40 c to +70 c) parameter symbol pin name condition value unit remarks min. max. valid address ? wr time t av wl a23 to a00 load condition: 80 pf t cyc /2 C 20 ns wr pulse width t wlwh wrl , wrh t cyc C 25 ns valid data output ? wr - time t dvwh d15 to d00 t cyc C 40 ns wr - ? data hold time t whdx d15 to d00 t cyc /2 C 20 ns wr - ? address valid time t whax a23 to a00 t cyc /2 C 20 ns wr ? clk time t wlcl wrl , wrh , clk t cyc /2 C 25 ns clk wr (wrl, wrh) a23 to a00 d15 to d00 read data 0.3 v cc 0.3 v cc 0.7 v cc 0.7 v cc 0.3 v cc 0.7 v cc 0.3 v cc 0.3 v cc 0.7 v cc 0.3 v cc 0.7 v cc indeter- minate t wlcl t wlwh t avwl t whax t whdx t dvwh
73 mb90220 series (7) ready input timing (v cc = +4.5 v to +5.5 v, v ss = 0.0 v, t a = C40 c to +70 c) note: use the auto-ready function if the rdy setup time is insufficient. (8) hold timing (v cc = +4.5 v to +5.5 v, v ss = 0.0 v, t a = C40 c to +70 c) note: it takes at least one machine cycle for hak to vary after hrq is fetched. parameter symbol pin name condition value unit remarks min. max. rdy setup time t ryhs rdy load condition: 80 pf 40 ns rdy hold time t ryhh rdy 0 ns parameter symbol pin name condition value unit remarks min. max. pin floating ? hak time t xhal hak load condition: 80 pf 30 t cyc ns hak - time ? pin valid time t hahv hak t cyc 2 t cyc ns a23 to a00 clk rd/wr (wrl, wrh) rdy no wait one wait t ryhh t ryhh 0.8 v cc 0.8 v cc 0.2 v cc 0.8 v cc 0.8 v cc 0.7 v cc 0.7 v cc t ryhs t ryhs hrq hak each pin high impedance 0.3 v cc 0.7 v cc 0.2 v cc 0.8 v cc t xhal t hahv
mb90220 series 74 (9) uart timing single-chip mode mb90223/224/p224b/w224b: (v cc = +4.5 v to +5.5 v, v ss = 0.0 v, t a = C40 c to +105 c) MB90P224A/w224a : (v cc = +4.5 v to +5.5 v, v ss = 0.0 v, t a = C40 c to +85 c) external bus mode : (v cc = +4.5 v to +5.5 v, v ss = 0.0 v, t a = C40 c to +70 c) notes: ? these ac characteristics assume in clk synchronization mode. ?t cyc is the machine cycle (unit: ns). parameter symbol pin name condition value unit remarks min. max. serial clock cycle time t scyc load condition: 80 pf 8 t cyc ns internal clock operation output pin sclk ? sout delay time t slov C80 80 ns valid sin ? sclk - t ivsh 100 ns sclk - ? valid sin hold time t shix 60ns serial clock h pulse width t shsl load condition: 80 pf 4 t cyc ns external clock operation output pin serial clock l pulse width t slsh 4 t cyc ns sclk ? sout delay time t slov 150 ns valid sin ? sclk - t ivsh 60ns sclk - ? valid sin hold time t shix 60ns
75 mb90220 series sod sck sid t slov t scyc t ivsh t shix sod sck sid t slov t slsh t ivsh t shix t shsl 0.3 v cc 0.3 v cc 0.7 v cc 0.7 v cc 0.3 v cc 0.8 v cc 0.2 v cc 0.8 v cc 0.2 v cc 0.2 v cc 0.2 v cc 0.8 v cc 0.8 v cc 0.7 v cc 0.3 v cc 0.8 v cc 0.2 v cc 0.8 v cc 0.2 v cc ? internal shift clock mode ? external shift clock input mode
mb90220 series 76 (10) resourse input timing single-chip mode mb90223/224/p224b/w224b: (v cc = +4.5 v to +5.5 v, v ss = 0.0 v, t a = C40 c to +105 c) MB90P224A/w224a : (v cc = +4.5 v to +5.5 v, v ss = 0.0 v, t a = C40 c to +85 c) external bus mode : (v cc = +4.5 v to +5.5 v, v ss = 0.0 v, t a = C40 c to +70 c) (11) resourse output timing single-chip mode mb90223/224/p224b/w224b: (v cc = +4.5 v to +5.5 v, v ss = 0.0 v, t a = C40 c to +105 c) MB90P224A/w224a : (v cc = +4.5 v to +5.5 v, v ss = 0.0 v, t a = C40 c to +85 c) external bus mode : (v cc = +4.5 v to +5.5 v, v ss = 0.0 v, t a = C40 c to +70 c) parameter symbol pin name condition value unit remarks min. typ. max. input pulse width t tiwh t tiwl tin1 to tin5 load condition: 80 pf 4 t cyc ns external event count input mode 2 t cyc ns trigger input/gate input mode pwc0 to pwc3 2 t cyc ns asr0 to asr3 2 t cyc ns int0 to int7 3 t cyc ns trg0 2 t cyc ns at g 2 t cyc ns t wiwl wi 4 t cyc ns parameter symbol pin name condition value unit remarks min. typ. max. clk - ? t out transition time t to tot0 to tot5 ppg0 to ppg1 pot0 to pot3 dot0 to dot7 load condition: 80 pf 30 ns 0.8 v cc 0.8 v cc 0.2 v cc 0.2 v cc tin1 to tin5 pwc0 to pwc3 asr0 to asr3 int0 to int7 wi trg0 atg t tiwh t tiwl , t wiwl clk t out t to 0.7 v cc 0.7 v cc 0.3 v cc
77 mb90220 series 5. a/d converter electrical characteristics single-chip mode mb90223/224/p224b/w224b : (av cc = v cc = +4.5 v to +5.5 v, av ss =v ss = 0.0 v, t a = C40 c to +105 c, +4.5 v avrh C avrl) MB90P224A/w224a : (av cc = v cc = +4.5 v to +5.5 v, av ss = v ss =0.0 v, t a = C40 c to +85 c, +4.5 v avrh C avrl) external bus mode : (av cc = v cc = +4.5 v to +5.5 v, av ss = v ss =0.0 v, t a = C40 c to +70 c, +4.5 v avrh C avrl) *1: these standards in this table are for mb90224/p224a/p224b/w224a/w224b. mb90223: minimum conversion time is 8.17 m s and minimum sampling time is 5 m s at t cyc = 83.4 ns. *2: the current value applies to the cpu stop mode with the a/d converter inactive (v cc = av cc = avrh = +5.5 v). notes: (1) the error becomes larger as | avrh C avrl | becomes smaller. (2) use the output impedance of the external circuit for analog input under the following conditions: external circuit output impedance < approx. 10 k w (sampling time approx. 3.75 m s, t cyc = 62.5 ns) (3) precision values are standard values applicable to sleep mode. (4) if v cc /av cc or v ss /av ss is caused by a noise to drop to below the analog input volgtage, the analog input current is likely to increase. in such cases, a bypass capacitor or the like should be provided in the external circuit to suppress the noise. parameter symbol pin name condition value unit remarks min. typ. max. resolution n 10 bit total error 3.0 lsb linearity error 2.0 lsb differential linearity error 1.5 lsb zero transition voltage v 0t an00 to an15 avrl C 1.5 avrl + 0.5 avrl + 2.5 lsb full-scale transition voltage v fst avrh C 3.5 avrh C 1.5 avrh + 0.5 lsb conversion time* 1 t conv t cyc = 62.5 ns 6.125 m s 98 machine cycles sampling period t samp 3.75 m s 60 machine cycles analog port input current i ain an00 to an15 0.1 m a analog input voltage v ain avrlavrhv analog reference voltage avrh avrl av cc v avrl av ss avrhv reference voltage supply current i r avrh 200 500 m a i rh 5* 2 m a variation between channels an00 to an15 4lsb
mb90220 series 78 6. a/d converter glossary resolution: analog changes that are identifiable with the a/d converter when the number of bits is 10, analog voltage can be divided into 2 10 = 1024. total error: difference between actual and logical values. this error is caused by a zero transition error, full-scale transition error, linearity error, differential linearity error, or by noise. linearity error: the deviation of the straight line connecting the zero transition point (00 0000 0000 ? 00 0000 0001) with the full-scale transition point (11 1111 1111 ? 11 1111 1110) from actual conversion characteristics differential linearity error: the deviation of input voltage needed to change the output code by 1 lsb from the theoretical value note: the values shown here are reference values. analog input comparator c 1 c 0 r on2 r on1 r on1 : approx. 1.5 k w r on2 : approx. 1.5 k w c 0 : approx. 60 pf c 1 : approx. 4 pf ? analog input circuit mode v fst v nt v 0t 1 lsb v fst ?v 0t 1022 = linearity error v nt ?(n 1 lsb + v 0t ) = 1 lsb differential linearity error v nt ?v (n?)t = 1 lsb total error digital output 11 1111 1111 11 1111 1110 11 1111 1101 00 0000 0010 00 0000 0001 00 0000 0000 ?1 v (n + 1)t n = 0 to 1022 v nt (n = 0) = v 0t v nt (n = 1022) = v fst n = 1 to 1022 n + 1 n n ?1 linearity error n 1lsb + v 0t v (n ?1)t v 1t v 2t theoretical value (v nt ) theoretical value actual conversion value avrl avrh (v) , 1 lsb theoretical value avrh ?avrl 1022 = total error v nt ?{(n + 0.5) 1 lsb theoretical value} = 1 lsb theoretical value n = 0 to 1022
79 mb90220 series n example characteristics (1) power supply current note: these are not assured value of characteristics but example characteristics. (2) output voltage note: these are not assured value of characteristics but example characteristics. 120 110 100 90 80 70 60 50 40 ?0 0 50 100 150 40 30 20 10 0 ?0 ?0 0 50 100 150 t a ( c) i cc (ma) i cch ( m a) t a ( c) i cc vs. t a example characteristics i cch vs. t a example characteristics fc = 16 mhz external clock input v cc = 5.0 v MB90P224A mb90223 v cc = 5 v 5.5 5.0 4.0 4.5 3.5 3.0 ?5 ?0 ? 0 5 v oh (v) i ol (ma) v oh vs. i oh example characteristics 2.0 1.5 0.5 1.0 0.0 ?.5 v ol (v) i oh (ma) v ol vs. i ol example characteristics ? 0 5 10 15 20 25 t a = +25 c v cc = 5.0 v t a = +25 c v cc = 5.0 v
mb90220 series 80 (3) pull-up/pull-down resistor note: these are not assured value of characteristics but example characteristics. (4) analog filter note: these are not assured value of characteristics but example characteristics. 100 90 80 70 60 50 40 30 20 ?0 0 50 100 150 ?0 0 50 100 150 t a ( c) r puld (k w )r pulu (k w ) t a ( c) pull-down resistor example characteristics pull-up resistor example characteristics v cc = 4.5 v v cc = 5.0 v v cc = 5.5 v v cc = 4.5 v v cc = 5.0 v v cc = 5.5 v 100 90 80 70 60 50 40 30 20 80 70 60 50 40 30 4.0 4.5 5.0 5.5 6.0 input pulse width (ns) analog filter example characteristics v cc ( v ) 20 10 filtering enable t a = +25 c
81 mb90220 series n instruction set (412 instructions) table 1 explanation of items in table of instructions item explanation mnemonic upper-case letters and symbols: represented as they appear in assembler lower-case letters: replaced when described in assembler. numbers after lower-case letters: indicate the bit width within the instruction. # indicates the number of bytes. ~ indicates the number of cycles. see table 4 for details about meanings of letters in items. b indicates the correction value for calculating the number of actual cycles during execution of instruction. the number of actual cycles during execution of instruction is summed with the value in the cycles column. operation indicates operation of instruction. lh indicates special operations involving the bits 15 through 08 of the accumulator. z: transfers 0. x: extends before transferring. : transfers nothing. ah indicates special operations involving the high-order 16 bits in the accumulator. *: transfers from al to ah. : no transfer. z: transfers 00 h to ah. x: transfers 00 h or ff h to ah by extending al. i indicates the status of each of the following flags: i (interrupt enable), s (stack), t (sticky bit), n (negative), z (zero), v (overflow), and c (carry). *: changes due to execution of instruction. : no change. s: set by execution of instruction. r: reset by execution of instruction. s t n z v c rmw indicates whether the instruction is a read-modify-write instruction (a single instruction that reads data from memory, etc., processes the data, and then writes the result to memory.). *: instruction is a read-modify-write instruction : instruction is not a read-modify-write instruction note: cannot be used for addresses that have different meanings depending on whether they are read or written.
mb90220 series 82 table 2 explanation of symbols in table of instructions (continued) symbol explanation a 32-bit accumulator the number of bits used varies according to the instruction. byte: low order 8 bits of al word: 16 bits of al long: 32 bits of al, ah ah high-order 16 bits of a al low-order 16 bits of a sp stack pointer (usp or ssp) pc program counter spcu stack pointer upper limit register spcl stack pointer lower limit register pcb program bank register dtb data bank register adb additional data bank register ssb system stack bank register usb user stack bank register spb current stack bank register (ssb or usb) dpr direct page register brg1 dtb, adb, ssb, usb, dpr, pcb, spb brg2 dtb, adb, ssb, usb, dpr, spb ri r0, r1, r2, r3, r4, r5, r6, r7 rwi rw0, rw1, rw2, rw3, rw4, rw5, rw6, rw7 rwj rw0, rw1, rw2, rw3 rli rl0, rl1, rl2, rl3 dir addr16 addr24 addr24 0 to 15 addr24 16 to 23 compact direct addressing direct addressing physical direct addressing bits 0 to 15 of addr24 bits 16 to 23 of addr24 io i/o area (000000 h to 0000ff h )
83 mb90220 series (continued) symbol explanation #imm4 #imm8 #imm16 #imm32 ext (imm8) 4-bit immediate data 8-bit immediate data 16-bit immediate data 32-bit immediate data 16-bit data signed and extended from 8-bit immediate data disp8 disp16 8-bit displacement 16-bit displacement bp bit offset value vct4 vct8 vector number (0 to 15) vector number (0 to 255) ( )b bit address rel ear eam branch specification relative to pc effective addressing (codes 00 to 07) effective addressing (codes 08 to 1f) rlst register list
mb90220 series 84 table 3 effective address fields * : the number of bytes for address extension is indicated by the + symbol in the # (number of bytes) column in the table of instructions. code notation address format number of bytes in address extemsion* 00 01 02 03 04 05 06 07 r0 r1 r2 r3 r4 r5 r6 r7 rw0 rw1 rw2 rw3 rw4 rw5 rw6 rw7 rl0 (rl0) rl1 (rl1) rl2 (rl2) rl3 (rl3) register direct ea corresponds to byte, word, and long-word types, starting from the left 08 09 0a 0b @rw0 @rw1 @rw2 @rw3 register indirect 0 0c 0d 0e 0f @rw0 + @rw1 + @rw2 + @rw3 + register indirect with post-increment 0 10 11 12 13 14 15 16 17 @rw0 + disp8 @rw1 + disp8 @rw2 + disp8 @rw3 + disp8 @rw4 + disp8 @rw5 + disp8 @rw6 + disp8 @rw7 + disp8 register indirect with 8-bit displacement 1 18 19 1a 1b @rw0 + disp16 @rw1 + disp16 @rw2 + disp16 @rw3 + disp16 register indirect with 16-bit displacemen 2 1c 1d 1e 1f @rw0 + rw7 @rw1 + rw7 @pc + dip16 addr16 register indirect with index register indirect with index pc indirect with 16-bit displacement direct address 0 0 2 2
85 mb90220 series table 4 number of execution cycles for each form of addressing * : (a) is used in the cycles (number of cycles) column and column b (correction value) in the table of instructions. table 5 correction values for number of cycles used to calculate number of actual cycles * : (b), (c), and (d) are used in the cycles (number of cycles) column and column b (correction value) in the table of instructions. code operand (a)* number of execution cycles for each from of addressing 00 to 07 ri rwi rli listed in table of instructions 08 to 0b @rwj 1 0c to 0f @rwj + 4 10 to 17 @rwi + disp8 1 18 to 1b @rwj + disp16 1 1c 1d 1e 1f @rw0 + rw7 @rw1 + rw7 @pc + dip16 @addr16 2 2 2 1 operand (b)* (c)* (d)* byte word long internal register + 0 + 0 + 0 internal ram even address + 0 + 0 + 0 internal ram odd address + 0 + 1 + 2 even address not in internal ram + 1 + 1 + 2 odd address not in internal ram + 1 + 3 + 6 external data bus (8 bits) + 1 + 3 + 6
mb90220 series 86 table 6 transfer instructions (byte) [50 instructions] (continued) mnemonic # cycles boperation lh ah istnzvc rmw mov a, dir mov a, addr16 mov a, ri mov a, ear mov a, eam mov a, io mov a, #imm8 mov a, @a mov a, @rli+disp8 mov a, @sp+disp8 movp a, addr24 movp a, @a movn a, #imm4 movx a, dir movx a, addr16 movx a, ri movx a, ear movx a, eam movx a, io movx a, #imm8 movx a, @a movx a,@rwi+disp8 movx a, @rli+disp8 movx a, @sp+disp8 movpx a, addr24 movpx a, @a mov dir, a mov addr16, a mov ri, a mov ear, a mov eam, a mov io, a mov @rli+disp8, a mov @sp+disp8, a movp addr24, a mov ri, ear mov ri, eam movp @a, ri mov ear, ri mov eam, ri mov ri, #imm8 mov io, #imm8 mov dir, #imm8 mov ear, #imm8 mov eam, #imm8 mov @al, ah 2 3 1 2 2+ 2 2 2 3 3 5 2 1 2 3 2 2 2+ 2 2 2 2 3 3 5 2 2 3 1 2 2+ 2 3 3 5 2 2+ 2 2 2+ 2 3 3 3 3+ 2 2 2 1 1 2+ (a) 2 2 2 6 3 3 2 1 2 2 1 1 2+ (a) 2 2 2 3 6 3 3 2 2 2 1 2 2+ (a) 2 6 3 3 2 3+ (a) 3 3 3+ (a) 2 3 3 2 2+ (a) 2 (b) (b) 0 0 (b) (b) 0 (b) (b) (b) (b) (b) 0 (b) (b) 0 0 (b) (b) 0 (b) (b) (b) (b) (b) (b) (b) (b) 0 0 (b) (b) (b) (b) (b) 0 (b) (b) 0 (b) 0 (b) (b) 0 (b) (b) byte (a) ? (dir) byte (a) ? (addr16) byte (a) ? (ri) byte (a) ? (ear) byte (a) ? (eam) byte (a) ? (io) byte (a) ? imm8 byte (a) ? ((a)) byte (a) ? ((rli))+disp8) byte (a) ? ((sp)+disp8) byte (a) ? (addr24) byte (a) ? ((a)) byte (a) ? imm4 byte (a) ? (dir) byte (a) ? (addr16) byte (a) ? (ri) byte (a) ? (ear) byte (a) ? (eam) byte (a) ? (io) byte (a) ? imm8 byte (a) ? ((a)) byte (a) ? ((rwi))+disp8) byte (a) ? ((rli))+disp8) byte (a) ? ((sp)+disp8) byte (a) ? (addr24) byte (a) ? ((a)) byte (dir) ? (a) byte (addr16) ? (a) byte (ri) ? (a) byte (ear) ? (a) byte (eam) ? (a) byte (io) ? (a) byte ((rli)) +disp8) ? (a) byte ((sp)+disp8) ? (a) byte (addr24) ? (a) byte (ri) ? (ear) byte (ri) ? (eam) byte ((a)) ? (ri) byte (ear) ? (ri) byte (eam) ? (ri) byte (ri) ? imm8 byte (io) ? imm8 byte (dir) ? imm8 byte (ear) ? imm8 byte (eam) ? imm8 byte ((a)) ? (ah) z z z z z z z z z z z z z x x x x x x x x x x x x x C C C C C C C C C C C C C C C C C C C C * * * * * * * C * * * C * * * * * * * * C * * * * C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * * * r * * * * * * * * * * * * * * * * * * * * * * * * * * * * C C * C * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * C C * C * C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C
87 mb90220 series (continued) for an explanation of (a) and (b), refer to table 4, number of execution cycles for each form of addressing, and table 5, correction values for number of cycles used to calculate number of actual cycles. mnemonic # cycles boperation lh ah istnzvc rmw xch a, ear xch a, eam xch ri, ear xch ri, eam 2 2+ 2 2+ 3 3+ (a) 4 5+ (a) 0 2 (b) 0 2 (b) byte (a) ? (ear) byte (a) ? (eam) byte (ri) ? (ear) byte (ri) ? (eam) z z C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C
mb90220 series 88 table 7 transfer instructions (word) [40 instructions] note: for an explanation of (a) and (c), refer to table 4, number of execution cycles for each form of addressing, and table 5, correction values for number of cycles used to calculate number of actual cycles. mnemonic # cycles boperation lh ah istnzvc rmw movw a, dir movw a, addr16 movw a, sp movw a, rwi movw a, ear movw a, eam movw a, io movw a, @a movw a, #imm16 movw a, @rwi+disp8 movw a, @rli+disp8 movw a, @sp+disp8 movpw a, addr24 movpw a, @a movw dir, a movw addr16, a movw sp, # imm16 movw sp, a movw rwi, a movw ear, a movw eam, a movw io, a movw @rwi+disp8, a movw @rli+disp8, a movw @sp+disp8, a movpw addr24, a movpw @a, rwi movw rwi, ear movw rwi, eam movw ear, rwi movw eam, rwi movw rwi, #imm16 movw io, #imm16 movw ear, #imm16 movw eam, #imm16 movw @al, ah xchw a, ear xchw a, eam xchw rwi, ear xchw rwi, eam 2 3 1 1 2 2+ 2 2 3 2 3 3 5 2 2 3 4 1 1 2 2+ 2 2 3 3 5 2 2 2+ 2 2+ 3 4 4 4+ 2 2 2+ 2 2+ 2 2 2 1 1 2+ (a) 2 2 2 3 6 3 3 2 2 2 2 2 1 2 2+ (a) 2 3 6 3 3 3 2 3+ (a) 3 3+ (a) 2 3 2 2+ (a) 2 3 3+ (a) 4 5+ (a) (c) (c) 0 0 0 (c) (c) (c) 0 (c) (c) (c) (c) (c) (c) (c) 0 0 0 0 (c) (c) (c) (c) (c) (c) (c) 0 (c) 0 (c) 0 (c) 0 (c) (c) 0 2 (c) 0 2 (c) word (a) ? (dir) word (a) ? (addr16) word (a) ? (sp) word (a) ? (rwi) word (a) ? (ear) word (a) ? (eam) word (a) ? (io) word (a) ? ((a)) word (a) ? imm16 word (a) ? ((rwi) +disp8) word (a) ? ((rli) +disp8) word (a) ? ((sp) +disp8 word (a) ? (addr24) word (a) ? ((a)) word (dir) ? (a) word (addr16) ? (a) word (sp) ? imm16 word (sp) ? (a) word (rwi) ? (a) word (ear) ? (a) word (eam) ? (a) word (io) ? (a) word ((rwi) +disp8) ? (a) word ((rli) +disp8) ? (a) word ((sp) +disp8) ? (a) word (addr24) ? (a) word ((a)) ? (rwi) word (rwi) ? (ear) word (rwi) ? (eam) word (ear) ? (rwi) word (eam) ? (rwi) word (rwi) ? imm16 word (io) ? imm16 word (ear) ? imm16 word (eam) ? imm16 word ((a)) ? (ah) word (a) ? (ear) word (a) ? (eam) word (rwi) ? (ear) word (rwi) ? (eam) C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * * * * * C * * * * * C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * C * C * C C C C * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * C * C * C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C
89 mb90220 series table 8 transfer instructions (long word) [11 instructions] for an explanation of (a) and (d), refer to table 4, number of execution cycles for each form of addressing, and table 5, correction values for number of cycles used to calculate number of actual cycles. mnemonic # cycles boperation lh ah istnzvc rmw movl a, ear movl a, eam movl a, # imm32 movl a, @sp + disp8 movpl a, addr24 movpl a, @a movpl @a, rli movl @sp + disp8, a movpl addr24, a movl ear, a movl eam, a 2 2+ 5 3 5 2 2 3 5 2 2+ 1 3+ (a) 3 4 4 3 5 4 4 2 3+ (a) 0 (d) 0 (d) (d) (d) (d) (d) (d) 0 (d) long (a) ? (ear) long (a) ? (eam) long (a) ? imm32 long (a) ? ((sp) +disp8) long (a) ? (addr24) long (a) ? ((a)) long ((a)) ? (rli) long ((sp) + disp8) ? (a) long (addr24) ? (a) long (ear) ? (a) long (eam) ? (a) C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * * * * * * * * * * * * * C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C
mb90220 series 90 table 9 addition and subtraction instructions (byte/word/long word) [42 instructions] for an explanation of (a), (b), (c) and (d), refer to table 4, number of execution cycles for each form of addressing, and table 5, correction values for number of cycles used to calculate number of actual cycles. mnemonic # cycles b operation lh ah istnzvc rmw add a, #imm8 add a, dir add a, ear add a, eam add ear, a add eam, a addc a addc a, ear addc a, eam adddc a sub a, #imm8 sub a, dir sub a, ear sub a, eam sub ear, a sub eam, a subc a subc a, ear subc a, eam subdc a 2 2 2 2+ 2 2+ 1 2 2+ 1 2 2 2 2+ 2 2+ 1 2 2+ 1 2 3 2 3+ (a) 2 3+ (a) 2 2 3+ (a) 3 2 3 2 3+ (a) 2 3+ (a) 2 2 3+ (a) 3 0 (b) 0 (b) 0 2 (b) 0 0 (b) 0 0 (b) 0 (b) 0 2 (b) 0 0 (b) 0 byte (a) ? (a) +imm8 byte (a) ? (a) +(dir) byte (a) ? (a) +(ear) byte (a) ? (a) +(eam) byte (ear) ? (ear) + (a) byte (eam) ? (eam) + (a) byte (a) ? (ah) + (al) + (c) byte (a) ? (a) + (ear) + (c) byte (a) ? (a) + (eam) + (c) byte (a) ? (ah) + (al) + (c) (decimal) byte (a) ? (a) Cimm8 byte (a) ? (a) C (dir) byte (a) ? (a) C (ear) byte (a) ? (a) C (eam) byte (ear) ? (ear) C (a) byte (eam) ? (eam) C (a) byte (a) ? (ah) C (al) C (c) byte (a) ? (a) C (ear) C (c) byte (a) ? (a) C (eam) C (c) byte (a) ? (ah) C (al) C (c) (decimal) z z z z C z z z z z z z z z C C z z z z C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * C C C C * * C C C C C C C C * * C C C C addw a addw a, ear addw a, eam addw a, #imm16 addw ear, a addw eam, a addcw a, ear addcw a, eam subw a subw a, ear subw a, eam subw a, #imm16 subw ear, a subw eam, a subcw a, ear subcw a, eam 1 2 2+ 3 2 2+ 2 2+ 1 2 2+ 3 2 2+ 2 2+ 2 2 3+ (a) 2 2 3+ (a) 2 3+ (a) 2 2 3+ (a) 2 2 3+ (a) 2 3+ (a) 0 0 (c) 0 0 2 (c) 0 (c) 0 0 (c) 0 0 2 (c) 0 (c) word (a) ? (ah) + (al) word (a) ? (a) +(ear) word (a) ? (a) +(eam) word (a) ? (a) +imm16 word (ear) ? (ear) + (a) word (eam) ? (eam) + (a) word (a) ? (a) + (ear) + (c) word (a) ? (a) + (eam) + (c) word (a) ? (ah) C (al) word (a) ? (a) C (ear) word (a) ? (a) C (eam) word (a) ? (a) Cimm16 word (ear) ? (ear) C (a) word (eam) ? (eam) C (a) word (a) ? (a) C (ear) C (c) word (a) ? (a) C (eam) C (c) C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * C C C C * * C C C C C C * * C C addl a, ear addl a, eam addl a, #imm32 subl a, ear subl a, eam subl a, #imm32 2 2+ 5 2 2+ 5 5 6+ (a) 4 5 6+ (a) 4 0 (d) 0 0 (d) 0 long (a) ? (a) + (ear) long (a) ? (a) + (eam) long (a) ? (a) +imm32 long (a) ? (a) C (ear) long (a) ? (a) C (eam) long (a) ? (a) Cimm32 C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * * * * * * * * * * * * * * * C C C C C C
91 mb90220 series table 10 increment and decrement instructions (byte/word/long word) [12 instructions] for an explanation of (a), (b), (c) and (d), refer to table 4, number of execution cycles for each form of addressing, and table 5, correction values for number of cycles used to calculate number of actual cycles. table 11 compare instructions (byte/word/long word) [11 instructions] for an explanation of (a), (b), (c) and (d), refer to table 4, number of execution cycles for each form of addressing, and table 5, correction values for number of cycles used to calculate number of actual cycles. mnemonic # cycles b operation lh ah istnzvc rmw inc ear inc eam dec ear dec eam 2 2+ 2 2+ 2 3+ (a) 2 3+ (a) 0 2 (b) 0 2 (b) byte (ear) ? (ear) +1 byte (eam) ? (eam) +1 byte (ear) ? (ear) C1 byte (eam) ? (eam) C1 C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * * * C C C C * * * * incw ear incw eam decw ear decw eam 2 2+ 2 2+ 2 3+ (a) 2 3+ (a) 0 2 (c) 0 2 (c) word (ear) ? (ear) +1 word (eam) ? (eam) +1 word (ear) ? (ear) C1 word (eam) ? (eam) C1 C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * * * C C C C * * * * incl ear incl eam decl ear decl eam 2 2+ 2 2+ 4 5+ (a) 4 5+ (a) 0 2 (d) 0 2 (d) long (ear) ? (ear) +1 long (eam) ? (eam) +1 long (ear) ? (ear) C1 long (eam) ? (eam) C1 C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * * * C C C C * * * * mnemonic # cycles b operation lh ah istnzvc rmw cmp a cmp a, ear cmp a, eam cmp a, #imm8 1 2 2+ 2 2 2 2+ (a) 2 0 0 (b) 0 byte (ah) C (al) byte (a) C (ear) byte (a) C (eam) byte (a) C imm8 C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * * * * * * * C C C C cmpw a cmpw a, ear cmpw a, eam cmpw a, #imm16 1 2 2+ 3 2 2 2+ (a) 2 0 0 (c) 0 word (ah) C (al) word (a) C (ear) word (a) C (eam) word (a) C imm16 C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * * * * * * * C C C C cmpl a, ear cmpl a, eam cmpl a, #imm32 2 2+ 5 3 4+ (a) 3 0 (d) 0 long (a) C (ear) long (a) C (eam) long (a) C imm32 C C C C C C C C C C C C C C C * * * * * * * * * * * * C C C
mb90220 series 92 table 12 unsigned multiplication and division instructions (word/long word) [11 instructions] for an explanation of (b) and (c), refer to table 5, correction values for number of cycle used to calculate number of actual cycles. *1: 3 when dividing into zero, 6 when an overflow occurs, and 14 normally. *2: 3 when dividing into zero, 5 when an overflow occurs, and 13 normally. *3: 5 + (a) when dividing into zero, 7 + (a) when an overflow occurs, and 17 + (a) normally. *4: 3 when dividing into zero, 5 when an overflow occurs, and 21 normally. *5: 4 + (a) when dividing into zero, 7 + (a) when an overflow occurs, and 25 + (a) normally. *6: (b) when dividing into zero or when an overflow occurs, and 2 (b) normally. *7: (c) when dividing into zero or when an overflow occurs, and 2 (c) normally. *8: 3 when byte (ah) is zero, and 7 when byte (ah) is not 0. *9: 3 when byte (ear) is zero, and 7 when byte (ear) is not 0. *10: 4 + (a) when byte (eam) is zero, and 8 + (a) when byte (eam) is not 0. *11: 3 when word (ah) is zero, and 11 when word (ah) is not 0. *12: 3 when word (ear) is zero, and 11 when word (ear) is not 0. *13: 4 + (a) when word (eam) is zero, and 12 + (a) when word (eam) is not 0. mnemonic # cycles b operation lh ah istnzvc rmw divu a divu a, ear divu a, eam divuw a, ear divuw a, eam mulu a mulu a, ear mulu a, eam muluw a muluw a, ear muluw a, eam 1 2 2+ 2 2+ 1 2 2+ 1 2 2+ * 1 * 2 * 3 * 4 * 5 * 8 * 9 * 10 * 11 * 12 * 13 0 0 * 6 0 * 7 0 0 (b) 0 0 (c) word (ah) /byte (al) quotient ? byte (al) remainder ? byte (ah) word (a)/byte (ear) quotient ? byte (a) remainder ? byte (ear) word (a)/byte (eam) quotient ? byte (a) remainder ? byte (eam) long (a)/word (ear) quotient ? word (a) remainder ? word (ear) long (a)/word (eam) quotient ? word (a) remainder ? word (eam) byte (ah) byte (al) ? word (a) byte (a) byte (ear) ? word (a) byte (a) byte (eam) ? word (a) word (ah) word (al) ? long (a) word (a) word (ear) ? long (a) word (a) word (eam) ? long (a) C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * * * C C C C C C * * * * * C C C C C C C C C C C C C C C C C
93 mb90220 series table 13 signed multiplication and division instructions (word/long word) [11 insturctions] for an explanation of (b) and (c), refer to table 5, correction values for number of cycles used to calculate number of actual cycles. *1: 3 when dividing into zero, 8 or 18 when an overflow occurs, and 18 normally. *2: 3 when dividing into zero, 10 or 21 when an overflow occurs, and 22 normally. *3: 4 + (a) when dividing into zero, 11 + (a) or 22 + (a) when an overflow occurs, and 23 + (a) normally. *4: when the dividend is positive: 4 when dividing into zero, 10 or 29 when an overflow occurs, and 30 normally. when the dividend is negative: 4 when dividing into zero, 11 or 30 when an overflow occurs, and 31 normally. *5: when the dividend is positive: 4 + (a) when dividing into zero, 11 + (a) or 30 + (a) when an overflow occurs, and 31 + (a) normally. when the dividend is negative: 4 + (a) when dividing into zero, 12 + (a) or 31 + (a) when an overflow occurs, and 32 + (a) normally. *6: (b) when dividing into zero or when an overflow occurs, and 2 (b) normally. *7: (c) when dividing into zero or when an overflow occurs, and 2 (c) normally. *8: 3 when byte (ah) is zero, 12 when the result is positive, and 13 when the result is negative. *9: 3 when byte (ear) is zero, 12 when the result is positive, and 13 when the result is negative. *10: 4 + (a) when byte (eam) is zero, 13 + (a) when the result is positive, and 14 + (a) when the result is negative. *11: 3 when word (ah) is zero, 12 when the result is positive, and 13 when the result is negative. *12: 3 when word (ear) is zero, 16 when the result is positive, and 19 when the result is negative. *13: 4 + (a) when word (eam) is zero, 17 + (a) when the result is positive, and 20 + (a) when the result is negative. note: which of the two values given for the number of execution cycles applies when an overflow error occurs in a div or divw instruction depends on whether the overflow was detected before or after the operation. mnemonic # cycles b operation lh ah istnzvc rmw div a div a, ear div a, eam divw a, ear divw a, eam 2 2 2+ 2 2+ * 1 * 2 * 3 * 4 * 5 0 0 * 6 0 * 7 word (ah) /byte (al) quotient ? byte (al) remainder ? byte (ah) word (a)/byte (ear) quotient ? byte (a) remainder ? byte (ear) word (a)/byte (eam) quotient ? byte (a) remainder ? byte (eam) long (a)/word (ear) quotient ? word (a) remainder ? word (ear) long (a)/word (eam) quotient ? word (a) remainder ? word (eam) z z z C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * C C C C C mul a mul a, ear mul a, eam mulw a mulw a, ear mulw a, eam 2 2 2+ 2 2 2+ * 8 * 9 * 10 * 11 * 12 * 13 0 0 (b) 0 0 (b) byte (ah) byte (al) ? word (a) byte (a) byte (ear) ? word (a) byte (a) byte (eam) ? word (a) word (ah) word (al) ? long (a) word (a) word (ear) ? long (a) word (a) word (eam) ? long (a) C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C
mb90220 series 94 table 14 logical 1 instructions (byte, word) [39 instructions] for an explanation of (a), (b), (c) and (d), refer to table 4, number of execution cycles for each form of addressing, and table 5, correction values for number of cycles used to calculate number of actual cycles. mnemonic # cycles b operation lh ah istnzvc rmw and a, #imm8 and a, ear and a, eam and ear, a and eam, a or a, #imm8 or a, ear or a, eam or ear, a or eam, a xor a, #imm8 xor a, ear xor a, eam xor ear, a xor eam, a not a not ear not eam 2 2 2+ 2 2+ 2 2 2+ 2 2+ 2 2 2+ 2 2+ 1 2 2+ 2 2 3+ (a) 3 3+ (a) 2 2 3+ (a) 3 3+ (a) 2 2 3+ (a) 3 3+ (a) 2 2 3+ (a) 0 0 (b) 0 2 (b) 0 0 (b) 0 2 (b) 0 0 (b) 0 2 (b) 0 0 2 (b) byte (a) ? (a) and imm8 byte (a) ? (a) and (ear) byte (a) ? (a) and (eam) byte (ear) ? (ear) and (a) byte (eam) ? (eam) and (a) byte (a) ? (a) or imm8 byte (a) ? (a) or (ear) byte (a) ? (a) or (eam) byte (ear) ? (ear) or (a) byte (eam) ? (eam) or (a) byte (a) ? (a) xor imm8 byte (a) ? (a) xor (ear) byte (a) ? (a) xor (eam) byte (ear) ? (ear) xor (a) byte (eam) ? (eam) xor (a) byte (a) ? not (a) byte (ear) ? not (ear) byte (eam) ? not (eam) C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * r r r r r r r r r r r r r r r r r r C C C C C C C C C C C C C C C C C C C C C * * C C C * * C C C * * C * * andw a andw a, #imm16 andw a, ear andw a, eam andw ear, a andw eam, a orw a orw a, #imm16 orw a, ear orw a, eam orw ear, a orw eam, a xorw a xorw a, #imm16 xorw a, ear xorw a, eam xorw ear, a xorw eam, a notw a notw ear notw eam 1 3 2 2+ 2 2+ 1 3 2 2+ 2 2+ 1 3 2 2+ 2 2+ 1 2 2+ 2 2 2 3+ (a) 3 3+ (a) 2 2 2 3+ (a) 3 3+ (a) 2 2 2 3+ (a) 3 3+ (a) 2 2 3+ (a) 0 0 0 (c) 0 2 (c) 0 0 0 (c) 0 2 (c) 0 0 0 (c) 0 2 (c) 0 0 2 (c) word (a) ? (ah) and (a) word (a) ? (a) and imm16 word (a) ? (a) and (ear) word (a) ? (a) and (eam) word (ear) ? (ear) and (a) word (eam) ? (eam) and (a) word (a) ? (ah) or (a) word (a) ? (a) or imm16 word (a) ? (a) or (ear) word (a) ? (a) or (eam) word (ear) ? (ear) or (a) word (eam) ? (eam) or (a) word (a) ? (ah) xor (a) word (a) ? (a) xor imm16 word (a) ? (a) xor (ear) word (a) ? (a) xor (eam) word (ear) ? (ear) xor (a) word (eam) ? (eam) xor (a) word (a) ? not (a) word (ear) ? not (ear) word (eam) ? not (eam) C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * r r r r r r r r r r r r r r r r r r r r r C C C C C C C C C C C C C C C C C C C C C C C C C * * C C C C * * C C C C * * C * *
95 mb90220 series table 15 logical 2 instructions (long word) [6 instructions] for an explanation of (a) and (d), refer to table 4, number of execution cycles for each form of addressing, and table 5, correction values for number of cycles used to calculate number of actual cycles. table 16 sign inversion instructions (byte/word) [6 instructions] for an explanation of (a), (b) and (c) and refer to table 4, number of execution cycles for each form of addressing, and table 5, correction values for number of cycles used to calculate number of actual cycles. table 17 absolute value instructions (byte/word/long word) [3 insturctions] table 18 normalize instructions (long word) [1 instruction] * : 5 when the contents of the accumulator are all zeroes, 5 + (r0) in all other cases. mnemonic # cycles b operation lh ah istnzvc rmw andl a, ear andl a, eam orl a, ear orl a, eam xorl a, ear xorl a, eam 2 2+ 2 2+ 2 2+ 5 6+ (a) 5 6+ (a) 5 6+ (a) 0 (d) 0 (d) 0 (d) long (a) ? (a) and (ear) long (a) ? (a) and (eam) long (a) ? (a) or (ear) long (a) ? (a) or (eam) long (a) ? (a) xor (ear) long (a) ? (a) xor (eam) C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * * * r r r r r r C C C C C C C C C C C C mnemonic # cycles b operation lh ah istnzvc rmw neg a neg ear neg eam 1 2 2+ 2 2 3+ (a) 0 0 2 (b) byte (a) ? 0 C (a) byte (ear) ? 0 C (ear) byte (eam) ? 0 C (eam) x C C C C C C C C C C C C C C * * * * * * * * * * * * C * * negw a negw ear negw eam 1 2 2+ 2 2 3+ (a) 0 0 2 (c) word (a) ? 0 C (a) word (ear) ? 0 C (ear) word (eam) ? 0 C (eam) C C C C C C C C C C C C C C C * * * * * * * * * * * * C * * mnemonic # cycles b operation lh ah istnzvc rmw abs a absw a absl a 2 2 2 2 2 4 0 0 0 byte (a) ? absolute value (a) word (a) ? absolute value (a) long (a) ? absolute value (a) z C C C C C C C C C C C C C C * * * * * * * * * C C C C C C mnemonic # cycles b operation lh ah istnzvc rmw nrml a, r0 2 * 0 long (a) ? shifts to the position at which 1 was set first byte (r0) ? current shift count CCCC*CCCC C
mb90220 series 96 table 19 shift instructions (byte/word/long word) [27 instructions] for an explanation of (a) and (b), refer to table 4, number of execution cycles for each form of addressing, and table 5, correction values for number of cycles used to calculate number of actual cycles. *1: 3 when r0 is 0, 3 + (r0) in all other cases. *2: 3 when r0 is 0, 4 + (r0) in all other cases. *3: 3 when imm8 is 0, 3 + (imm8) in all other cases. *4: 3 when imm8 is 0, 4 + (imm8) in all other cases. mnemonic # cycles b operation lh ah istnzvc rmw rorc a rolc a rorc ear rorc eam rolc ear rolc eam asr a, r0 lsr a, r0 lsl a, r0 asr a, #imm8 lsr a, #imm8 lsl a, #imm8 2 2 2 2+ 2 2+ 2 2 2 3 3 3 2 2 2 3+ (a) 2 3+ (a) * 1 * 1 * 1 * 3 * 3 * 3 0 0 0 2 (b) 0 2 (b) 0 0 0 0 0 0 byte (a) ? right rotation with carry byte (a) ? left rotation with carry byte (ear) ? right rotation with carry byte (eam) ? right rotation with carry byte (ear) ? left rotation with carry byte (eam) ? left rotation with carry byte (a) ? arithmetic right barrel shift (a, r0) byte (a) ? logical right barrel shift (a, r0) byte (a) ? logical left barrel shift (a, r0) byte (a) ? arithmetic right barrel shift (a, imm8) byte (a) ? logical right barrel shift (a, imm8) byte (a) ? logical left barrel shift (a, imm8) C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * C * * C * * * * * * * * * * * * * * * * * * * * * * * * C C C C C C C C C C C C * * * * * * * * * * * * C C * * * * C C C C C C asrw a lsrw a/shrw a lslw a/shlw a asrw a, r0 lsrw a, r0 lslw a, r0 asrw a, #imm8 lsrw a, #imm8 lslw a, #imm8 1 1 1 2 2 2 3 3 3 2 2 2 * 1 * 1 * 1 * 3 * 3 * 3 0 0 0 0 0 0 0 0 0 word (a) ? arithmetic right shift (a, 1 bit) word (a) ? logical right shift (a, 1 bit) word (a) ? logical left shift (a, 1 bit) word (a) ? arithmetic right barrel shift (a, r0) word (a) ? logical right barrel shift (a, r0) word (a) ? logical left barrel shift (a, r0) word (a) ? arithmetic right barrel shift (a, imm8) word (a) ? logical right barrel shift (a, imm8) word (a) ? logical left barrel shift (a, imm8) C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * C * * C * * C * r * * * * * * * * * * * * * * * * C C C C C C C C C * * * * * * * * * C C C C C C C C C asrl a, r0 lsrl a, r0 lsll a, r0 asrl a, #imm8 lsrl a, #imm8 lsll a, #imm8 2 2 2 3 3 3 * 2 * 2 * 2 * 4 * 4 * 4 0 0 0 0 0 0 long (a) ? arithmetic right shift (a, r0) long (a) ? logical right barrel shift (a, r0) long (a) ? logical left barrel shift (a, r0) long (a) ? arithmetic right shift (a, imm8) long (a) ? logical right barrel shift (a, imm8) long (a) ? logical left barrel shift (a, imm8) C C C C C C C C C C C C C C C C C C C C C C C C * * C * * C * * * * * * * * * * * * C C C C C C * * * * * * C C C C C C
97 mb90220 series table 20 branch 1 instructions [31 instructions] for an explanation of (a), (c) and (d), refer to table 4, number of execution cycles for each form of addressing, and table 5, correction values for number of cycles used to calculate number of actual cycles. *1: 3 when branching, 2 when not branching. *2: 3 (c) + (b) *3: read (word) branch address. *4: w: save (word) to stack; r: read (word) branch address. *5: save (word) to stack. *6: w: save (long word) to w stack; r: read (long word) branch address. *7: save (long word) to stack. mnemonic # cycles b operation lh ah istnzvc rmw bz/beq rel bnz/bne rel bc/blo rel bnc/bhs rel bn rel bp rel bv rel bnv rel bt rel bnt rel blt rel bge rel ble rel bgt rel bls rel bhi rel bra rel jmp @a jmp addr16 jmp @ear jmp @eam jmpp @ear * 3 jmpp @eam * 3 jmpp addr24 call @ear * 4 call @eam * 4 call addr16 * 5 callv #vct4 * 5 callp @ear * 6 callp @eam * 6 callp addr24 * 7 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 3 2 2+ 2 2+ 4 2 2+ 3 1 2 2+ 4 * 1 * 1 * 1 * 1 * 1 * 1 * 1 * 1 * 1 * 1 * 1 * 1 * 1 * 1 * 1 * 1 * 1 2 2 3 4+ (a) 3 4+ (a) 3 4 5+ (a) 5 5 7 8+ (a) 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (c) 0 (d) 0 (c) 2 (c) (c) 2 (c) 2 (c) * 2 2 (c) branch when (z) = 1 branch when (z) = 0 branch when (c) = 1 branch when (c) = 0 branch when (n) = 1 branch when (n) = 0 branch when (v) = 1 branch when (v) = 0 branch when (t) = 1 branch when (t) = 0 branch when (v) xor (n) = 1 branch when (v) xor (n) = 0 ( (v) xor (n) ) or (z) = 1 ( (v) xor (n) ) or (z) = 0 branch when (c) or (z) = 1 branch when (c) or (z) = 0 branch unconditionally word (pc) ? (a) word (pc) ? addr16 word (pc) ? (ear) word (pc) ? (eam) word (pc) ? (ear), (pcb) ? (ear +2) word (pc) ? (eam), (pcb) ? (eam +2) word (pc) ? ad24 0 to 15 (pcb) ? ad24 16 to 23 word (pc) ? (ear) word (pc) ? (eam) word (pc) ? addr16 vector call linstruction word (pc) ? (ear) 0 to 15, (pcb) ? (ear) 16 to 23 word (pc) ? (eam) 0 to 15, (pcb) ? (eam) 16 to 23 word (pc) ? addr 0 to 15, (pcb) ? addr 16 to 23 C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C
mb90220 series 98 table 21 branch 2 instructions [20 instructions] for an explanation of (b), (c) and (d), refer to table 5, correction values for number of cycles used to calculate number of actual cycles. *1: 4 when branching, 3 when not branching *2: 5 when branching, 4 when not branching *3: 5 + (a) when branching, 4 + (a) when not branching *4: 6 + (a) when branching, 5 + (a) when not branching *5: 3 (b) + 2 (c) when an interrupt request is generated, 6 (c) when returning from the interrupt. *6: high-speed interrupt return instruction. when an interrupt request is detected during this instruction, the instruction branches to the interrupt vector without performing stack operations when the interrupt is generated. *7: return from stack (word) *8: return from stack (long word) mnemonic # cycles b operation lh ah istnzvc rmw cbne a, #imm8, rel cwbne a, #imm16, rel cbne ear, #imm8, rel cbne eam, #imm8, rel cwbne ear, #imm16, rel cwbne eam, #imm16, rel dbnz ear, rel dbnz eam, rel dwbnz ear, rel dwbnz eam, rel int #vct8 int addr16 intp addr24 int9 reti retiq * 6 link #imm8 unlink ret * 7 retp * 8 3 4 4 4+ 5 5+ 3 3+ 3 3+ 2 3 4 1 1 2 2 1 1 1 * 1 * 1 * 1 * 3 * 1 * 3 * 2 * 4 * 2 * 4 14 12 13 14 9 11 6 5 4 5 0 0 0 (b) 0 (c) 0 2 (b) 0 2 (c) 8 (c) 6 (c) 6 (c) 8 (c) 6 (c) * 5 (c) (c) (c) (d) branch when byte (a) 1 imm8 branch when byte (a) 1 imm16 branch when byte (ear) 1 imm8 branch when byte (eam) 1 imm8 branch when word (ear) 1 imm16 branch when word (eam) 1 imm16 branch when byte (ear) = (ear) C 1, and (ear) 1 0 branch when byte (ear) = (eam) C 1, and (eam) 1 0 branch when word (ear) = (ear) C 1, and (ear) 1 0 branch when word (eam) = (eam) C 1, and (eam) 1 0 software interrupt software interrupt software interrupt software interrupt return from interrupt return from interrupt at constant entry, save old frame pointer to stack, set new frame pointer, and allocate local pointer area at constant entry, retrieve old frame pointer from stack. return from subroutine return from subroutine C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C r r r r * * C C C C C C C C C C C C C C s s s s * * C C C C C C C C C C C C C C C C C C * * C C C C * * * * * * * * * * C C C C * * C C C C * * * * * * * * * * C C C C * * C C C C * * * * * * * * * * C C C C * * C C C C * * * * * * C C C C C C C C * * C C C C C C C C C C C * C * C C C C C C C C C C
99 mb90220 series table 22 other control instructions (byte/word/long word) [36 instructions] for an explanation of (a) and (c), refer to tables 4 and 5. *1: pcb, adb, ssb, usb, and spb: 1 cycle *4: pop count (c), or push count (c) dtb: 2 cycles *5: 3 when al is 0, 5 when al is not 0. dpr: 3 cycles *6: 4 when al is 0, 6 when al is not 0. *2: 3 + 4 (pop count) *7: 5 when al is 0, 7 when al is not 0. *3: 3 + 4 (push count) mnemonic # cycles b operation lh ah istnzvc rmw pushw a pushw ah pushw ps pushw rlst popw a popw ah popw ps popw rlst jctx @a and ccr, #imm8 or ccr, #imm8 mov rp, #imm8 mov ilm, #imm8 movea rwi, ear movea rwi, eam movea a, ear movea a, eam addsp #imm8 addsp #imm16 mov a, brgl mov brg2, a mov brg2, #imm8 nop adb dtb pcb spb ncc cmr movw spcu, #imm16 movw spcl, #imm16 setspc clrspc btscn a btscns a btscnd a 1 1 1 2 1 1 1 2 1 2 2 2 2 2 2+ 2 2+ 2 3 2 2 3 1 1 1 1 1 1 1 4 4 2 2 2 2 2 3 3 3 * 3 3 3 3 * 2 9 3 3 2 2 3 2+ (a) 2 1+ (a) 3 3 * 1 1 2 1 1 1 1 1 1 1 2 2 2 2 * 5 * 6 * 7 (c) (c) (c) * 4 (c) (c) (c) * 4 6 (c) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 word (sp) ? (sp) C2, ((sp)) ? (a) word (sp) ? (sp) C2, ((sp)) ? (ah) word (sp) ? (sp) C2, ((sp)) ? (ps) (sp) ? (sp) C2n, ((sp)) ? (rlst) word (a) ? ((sp)), (sp) ? ( sp) +2 word (ah) ? ((sp)), (sp) ? ( sp) +2 word (ps) ? ((sp)), (sp) ? ( sp) +2 (rlst) ? ((sp)) , (sp) ? (sp) context switch instruction byte (ccr) ? (ccr) and imm8 byte (ccr) ? (ccr) or imm8 byte (rp) ? imm8 byte (ilm) ? imm8 word (rwi) ? ear word (rwi) ? eam word(a) ? ear word (a) ? eam word (sp) ? ext (imm8) word (sp) ? imm16 byte (a) ? (brgl) byte (brg2) ? (a) byte (brg2) ? imm8 no operation prefix code for ad space access prefix code for dt space access prefix code for pc space access prefix code for sp space access prefix code for no flag change prefix code for the common register bank word (spcu) ? (imm16) word (spcl) ? (imm16) stack check ooperation enable stack check ooperation disable byte (a) ? position of 1 bit in word (a) byte (a) ? position of 1 bit in word (a) 2 byte (a) ? position of 1 bit in word (a) 4 C C C C C C C C C C C C C C C C C C C z C C C C C C C C C C C C C z z z C C C C * C C C C C C C C C C * * C C * C C C C C C C C C C C C C C C C C C C C C C * C * * * C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * C * * * C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * C * * * C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * C * * * C C C C C C C C * * * C C C C C C C C C C C C C C C C C C C C * C * * * C C C C C C C C * * * C C C C C C C C C C C * * * C C C C C C * C * * * C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * C * * * C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C
mb90220 series 100 table 23 bit manipulation instructions [21 instructions] for an explanation of (b), refer to table 5, correction values for number of cycles used to calculate number of actual cycles. *1: 5 when branching, 4 when not branching *2: 7 when condition is satisfied, 6 when not satisfied *3: undefined count *4: until condition is satisfied mnemonic # cycles b operation lh ah istnzvc rmw movb a, dir:bp movb a, addr16:bp movb a, io:bp movb dir:bp, a movb addr16:bp, a movb io:bp, a setb dir:bp setb addr16:bp setb io:bp clrb dir:bp clrb addr16:bp clrb io:bp bbc dir:bp, rel bbc addr16:bp, rel bbc io:bp, rel bbs dir:bp, rel bbs addr16:bp, rel bbs io:bp, rel sbbs addr16:bp, rel wbts io:bp wbtc io:bp 3 4 3 3 4 3 3 4 3 3 4 3 4 5 4 4 5 4 5 3 3 3 3 3 4 4 4 4 4 4 4 4 4 * 1 * 1 * 1 * 1 * 1 * 1 * 2 * 3 * 3 (b) (b) (b) 2 (b) 2 (b) 2 (b) 2 (b) 2 (b) 2 (b) 2 (b) 2 (b) 2 (b) (b) (b) (b) (b) (b) (b) 2 (b) * 4 * 4 byte (a) ? (dir:bp) b byte (a) ? (addr16:bp) b byte (a) ? (io:bp) b bit (dir:bp) b ? (a) bit (addr16:bp) b ? (a) bit (io:bp) b ? (a) bit (dir:bp) b ? 1 bit (addr16:bp) b ? 1 bit (io:bp) b ? 1 bit (dir:bp) b ? 0 bit (addr16:bp) b ? 0 bit (io:bp) b ? 0 branch when (dir:bp) b = 0 branch when (addr16:bp) b = 0 branch when (io:bp) b = 0 branch when (dir:bp) b = 1 branch when (addr16:bp) b = 1 branch when (io:bp) b = 1 branch when (addr16:bp) b = 1, bit = 1 wait until (io:bp) b = 1 wait until (io:bp) b = 0 z z z C C C C C C C C C C C C C C C C C C * * * C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * * * * C C C C C C C C C C C C C C C * * * * * * C C C C C C * * * * * * * C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * * * * * * * C C C C C C * C C
101 mb90220 series table 24 accumulator manipulation instructions (byte/word) [6 instructions] table 25 string instructions [10 instructions] m: rw0 value (counter value) *1: 3 when rw0 is 0, 2 + 6 (rw0) for count out, and 6n + 4 when match occurs *2: 4 when rw0 is 0, 2 + 6 (rw0) in any other case *3: (b) (rw0) *4: (b) n *5: (b) (rw0) *6: (c) (rw0) *7: (c) n *8: (c) (rw0) mnemonic # cycles b operation lh ah istnzvc rmw swap swapw ext extw zext zextw 1 1 1 1 1 1 3 2 1 2 1 2 0 0 0 0 0 0 byte (a) 0 to 7 ? ? (a) 8 to 15 word (ah) ? ? (al) byte code extension word code extension byte zero extension word zero extension C C x C z C C * C x C z C C C C C C C C C C C C C C C C C C C C * * r r C C * * * * C C C C C C C C C C C C C C C C C C mnemonic # cycles b operation lh ah istnzvc rmw movs/movsi movsd sceq/sceqi sceqd fils/filsi 2 2 2 2 2 * 2 * 2 * 1 * 1 5m +3 * 3 * 3 * 4 * 4 * 5 byte transfer @ah+ ? @al+, counter = rw0 byte transfer @ahC ? @alC, counter = rw0 byte retrieval @ah+ C al, counter = rw0 byte retrieval @ahC C al, counter = rw0 byte filling @ah+ ? al, counter = rw0 C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * C C * * * C C * * C C C * * C C C C C C movsw/movswi movswd scweq/scweqi scweqd filsw/filswi 2 2 2 2 2 * 2 * 2 * 1 * 1 5m +3 * 6 * 6 * 7 * 7 * 8 word transfer @ah+ ? @al+, counter = rw0 word transfer @ahC ? @alC, counter = rw0 word retrieval @ah+ C al, counter = rw0 word retrieval @ahC C al, counter = rw0 word filling @ah+ ? al, counter = rw0 C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * C C * * * C C * * C C C * * C C C C C C
mb90220 series 102 table 26 multiple data transfer instructions [18 instructions] *1: 5 + imm8 5, 256 times when imm8 is zero. *2: 5 + imm8 5 + (a), 256 times when imm8 is zero. *3: number of transfers (b) 2 *4: number of transfers (c) 2 *5: the bank register specified by bnk is the same as for the movs instruction. mnemonic # cycles b operation lh ah istnzvc rmw movm @a, @rli, #imm8 movm @a, eam, #imm8 movm addr16, @rli, #imm8 movm addr16, eam, #imm8 movmw @a, @rli, #imm8 movmw @a, eam, #imm8 movmw addr16, @rli, #imm8 movmw addr16, eam, #imm8 movm @rli, @a, #imm8 movm eam, @a, #imm8 movm @rli, addr16, #imm8 movm eam, addr16, #imm8 movmw @rli, @a, #imm8 movmw eam, @a, #imm8 movmw@rli, addr16, #imm8 movmw eam, addr16, #imm8 movm bnk : addr16, * 5 bnk : addr16, #imm8 movmw bnk : addr16, * 5 bnk : addr16, #imm8 3 3+ 5 5+ 3 3+ 5 5+ 3 3+ 5 5+ 3 3+ 5 5+ 7 7 * 1 * 2 * 1 * 2 * 1 * 2 * 1 * 2 * 1 * 2 * 1 * 2 * 1 * 2 * 1 * 2 * 1 * 1 * 3 * 3 * 3 * 3 * 4 * 4 * 4 * 4 * 3 * 3 * 3 * 3 * 4 * 4 * 4 * 4 * 3 * 4 multiple data trasfer byte ((a)) ? ((rli)) multiple data trasfer byte ((a)) ? (eam) multiple data trasfer byte (addr16) ? ((rli)) multiple data trasfer byte (addr16) ? (eam) multiple data trasfer word ((a)) ? ((rli)) multiple data trasfer word ((a)) ? (eam) multiple data trasfer word (addr16) ? ((rli)) multiple data trasfer word (addr16) ? (eam) multiple data trasfer byte ((rli)) ? ((a)) multiple data trasfer byte (eam) ? ((a)) multiple data transfer byte ((rli)) ? (addr16) multiple data transfer byte (eam) ? (addr16) multiple data trasfer word ((rli)) ? ((a)) multiple data trasfer word (eam) ? ((a)) multiple data transfer word ((rli)) ? (addr16) multiple data transfer word (eam) ? (addr16) multiple data transfer byte (bnk:addr16) ? (bnk:addr16) multiple data transfer word (bnk:addr16) ? (bnk:addr16) C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C
101 mb90220 series n ordering information part number type package remarks mb90224 mb90223 MB90P224A mb90p224b mb90224pf mb90223pf mb90p224pf mb90p224bpf 120-pin plastic qfp (fpt-120p-m03) mb90w224a mb90w224b mb90w224zf mb90w224bzf 120-pin ceramic qfp (fpt-120c-c02) es level only mb90v220 mb90v220cr 256-pin ceramic pga (pga-256c-a02) for evaluation
mb90220 series 104 n package dimensions note: see to the latest version of package data book for official package dimensions. +0.60 C0.30 +.023 C.012 "a" 1.450.20(.057.008) 0.150.05(.006.002) details of "a" part 0~10 0 (stand off) 0.05(.002)min 3.55(.140)max (.0315.008) 0.800.20 0.10(.004) sq (1.197.010) 30.400.25 index area (.0138.0040) 0.350.10 0.80(.0315)typ ?12.70(.0500)ref 32.000.30(1.260.012)sq sq 28.00 1.102 23.20(.9135)ref 1994 fujitsu limited f120023sc-1-1 c 0.20(.008) 0.25(.010) 0.18(.007)max 0.58(.023)max 90 91 61 60 120 index 31 30 lead no. 1 0.10(.004) m 0.16(.006) (.014.004) 0.350.10 0.80(.0315)typ (.006.002) 0.150.05 ref (.913) 23.20 (1.197.016) 30.400.40 (stand off) 0(0)min 3.85(.152)max 28.000.20(1.102.008)sq 32.000.40(1.260.016)sq "b" "a" 0 10 0.800.20(.031.008) details of "b" part details of "a" part 1994 fujitsu limited f120004s-3c-2 c dimensions in mm (inches) 120-pin plastic qfp (fpt-120p-m03) 120-pin ceramic qfp (fpt-120c-c02) dimensions in mm (inches)
105 mb90220 series fujitsu limited for further information please contact: japan fujitsu limited corporate global business support division electronic devices kawasaki plant, 4-1-1, kamikodanaka nakahara-ku, kawasaki-shi kanagawa 211-88, japan tel: (044) 754-3763 fax: (044) 754-3329 http://www.fujitsu.co.jp/ north and south america fujitsu microelectronics, inc. semiconductor division 3545 north first street san jose, ca 95134-1804, u.s.a. tel: (408) 922-9000 fax: (408) 922-9179 customer response center mon. - fri.: 7 am - 5 pm (pst) tel: (800) 866-8608 fax: (408) 922-9179 http://www.fujitsumicro.com/ europe fujitsu mikroelektronik gmbh am siebenstein 6-10 d-63303 dreieich-buchschlag germany tel: (06103) 690-0 fax: (06103) 690-122 http://www.fujitsu-ede.com/ asia pacific fujitsu microelectronics asia pte ltd #05-08, 151 lorong chuan new tech park singapore 556741 tel: (65) 281-0770 fax: (65) 281-0220 http://www.fmap.com.sg/ f9710 ? fujitsu limited printed in japan all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information and circuit diagrams in this document presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. also, fujitsu is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. fujitsu semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). caution: customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with fujitsu sales representatives before such use. the company will not be responsible for damages arising from such use without prior approval. any semiconductor devices have inherently a certain rate of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade control law of japan, the prior authorization by japanese government should be required for export of those products from japan.

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